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The following topics are dealt with: modified floating gate, NAND flash memory, carrier mobility, ion implantation, continuous anodic oxidation, differential Hall effect, dielectric films, high voltage isolation device, nanowire FET, sigma-delta modulator, all digital multiplying DLL, precision digital delay line, proximity communication, DC coupled sensor amplifier, offset cancellation, column-parallel...
A methodology is established to correlate shifts of test structure device parameters, due to device degradation or process variation, to circuit operation throughout the product lifetime. To the authors' knowledge, this work is original in that SPICE simulation is used, with degraded device models, to relate a circuit timing metric to the degradation of a discrete device used in the circuit. The correlation...
In this paper all digital multiplying delay-locked loop (MDLL) is presented, which uses a 3rd order precision digital delay line (HDL) as DCO. Maximum locking frequency at 1.3 V was 1 GHz with multiplication factor of 50, assuming 20 MHz reference clock frequency, and peak to peak jitter was ?? 61617; 20ps. DCO consumed only 2.2 mW, and the rest logic 3.5 mW.
A novel depletion mode high voltage isolation device is presented. It consists of a narrow n- resistor covered with a grounded metal field plate. This device will pass low voltages, but will block high voltages. It has potential application to isolate a NAND memory array from periphery low voltage circuitry, and has the benefit that it can be made more compact than a standard MOSFET device and can...
New carrier mobility (??) data for boron-, phosphorus-, and arsenic-doped Si in a low-energy, high-dose implant regime are measured and studied using continuous anodic oxidation technique/differential Hall effect (CAOT/DHE) technique. The data show that when the doping concentration is > 1020/cm3, both hole and electron mobility values are lower than the conventional model predictions, and the...
We report a new approach to utilize oxygen implantation on the top of the floating gate (FG) to improve the cell performance of a sub-50 nm NAND flash memory cell. This method was used to form a thin oxide layer only on the top of the FG but not on the sidewalls. It also rounded the corners of the FG. As a result, the leakage current between FG and control gate (CG) was reduced without sacrificing...
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