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New carrier mobility (??) data for boron-, phosphorus-, and arsenic-doped Si in a low-energy, high-dose implant regime are measured and studied using continuous anodic oxidation technique/differential Hall effect (CAOT/DHE) technique. The data show that when the doping concentration is > 1020/cm3, both hole and electron mobility values are lower than the conventional model predictions, and the...
We report a new approach to utilize oxygen implantation on the top of the floating gate (FG) to improve the cell performance of a sub-50 nm NAND flash memory cell. This method was used to form a thin oxide layer only on the top of the FG but not on the sidewalls. It also rounded the corners of the FG. As a result, the leakage current between FG and control gate (CG) was reduced without sacrificing...
A methodology is established to correlate shifts of test structure device parameters, due to device degradation or process variation, to circuit operation throughout the product lifetime. To the authors' knowledge, this work is original in that SPICE simulation is used, with degraded device models, to relate a circuit timing metric to the degradation of a discrete device used in the circuit. The correlation...
In this paper all digital multiplying delay-locked loop (MDLL) is presented, which uses a 3rd order precision digital delay line (HDL) as DCO. Maximum locking frequency at 1.3 V was 1 GHz with multiplication factor of 50, assuming 20 MHz reference clock frequency, and peak to peak jitter was ?? 61617; 20ps. DCO consumed only 2.2 mW, and the rest logic 3.5 mW.
A new analog-to-digital converter (ADC) technology called Single-slope look ahead ramp (SSLAR) analog-to-digital converter (ADC) was proposed for column-parallel CMOS image sensors. Additionally, a corresponding programmable ramp generator for SSLAR ADC was also designed in such a way that it only allows flexible code hopping (between 0 and 127 least significant bit (LSB)), code fall back and look-ahead...
This paper reports transistor-level design of a new continuous-time (CT), discrete-time (DT) cascaded sigma delta modulator (SDM). The combination of a CT first stage and a DT second stage was utilized to realize a high speed, high resolution analog-to-digital converter (ADC). Power consumption of CT first stage is lowered by optimizing the gain coefficients of CT integrators in a feedforward topology...
The following topics are dealt with: modified floating gate, NAND flash memory, carrier mobility, ion implantation, continuous anodic oxidation, differential Hall effect, dielectric films, high voltage isolation device, nanowire FET, sigma-delta modulator, all digital multiplying DLL, precision digital delay line, proximity communication, DC coupled sensor amplifier, offset cancellation, column-parallel...
Ultra-scaled SiGe nanowire FETs (NWFETs) are an attractive candidate in achieving faster p-type devices compared to Silicon. This work investigates the performance of SiGe nanowire FETs (NWFETs) using a Virtual Crystal Approximation (VCA) method based on an atomistic Tight-Binding (TB) model. The electronic structure calculation is self- consistently coupled to a 2D Poisson solver. The spatial charge...
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