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The paper presents a 24 V chopper offset-stabilized operational amplifier with symmetrical RC notch filters, having a 4–24 V supply range, and being realized using a 0.25 ßm BCD process. The amplifier has a typical offset voltage of 1.2 μV, a minimum PSRR of 128 dB, a minimum CMRR of 120 dB, a minimum open-loop gain of 134dB, a noise PSD of 30 nV/√Hz, 1.8 MHz unity gain bandwidth, and THD + noise...
This paper presents a constant bandwidth switched-capacitor programmable-gain amplifier (SC-PGA). By using an adaptive Miller compensation technique for the SC-PGA, our SC-PGA achieves low power consumption and high linearity at various gain conditions. The post-layout simulation results with 0.18 μm CMOS process show that power efficiency is tripled over the SC-PGA without the adaptive Miller compensation...
A switched capacitor low-side current sensing signal conditioning circuit with high dynamic range is demonstrated in AMS 0.35 μm, 3.3 V CMOS process. The design incorporates a Switched Capacitor Programmable Gain Amplifier (SC-PGA) and multi-bit second order ΔΣ-ADC. The switched capacitor eliminates the need for explicit level-shifting and chopping circuits thus facilitating sensing of input signal...
High resolution pipelined Analog-to-Digital Converters (ADCs) exceeding 10-bits are thermal noise limited. Typically for low-power switched capacitor (SC) circuits, the thermal noise of the op amp is the dominant source of noise as compared to the switches. This paper proposes a thermal noise canceling technique for pipelined stages that cancels the thermal noise of the op amp. The technique involves...
In this paper a design of two-stage CMOS operational amplifier for sigma-delta ADC is presented, which operates at ±1.8 V power supply using 180 nm technology. This two-stage CMOS OP-AMP has been designed to indicate a unity gain frequency of 18.2MHz and indicates a gain of 71.27 dB. The design and simulation part has been done on Cadence Custom IC CAD. The simulated results are encouraging and has...
In this paper a CMOS operational amplifier is presented. A CMOS operational amplifier is presented here which is operating at 2V power supply and 1microamp input bias current at 0.8micrometer technology using nonconventional mode of MOS transistors and whose input is dependent on bias current. The unique behavior of the MOS transistors in sub threshold region allows a designer to work at low input...
This paper proposes a hardware optimized low power three stage compensated operational amplifier with a capability of driving a wide range of capacitive loads ranging from 200pF to 5nF. The amplifier is compensated by implementing Embedded Capacitance Multiplier (CM) Compensation on the outer Miller capacitor of traditional Reverse Nested Miller Compensation (RNMC) with a feed forward stage. This...
This paper proposes a full speed digital gain error calibration technique for pipelined ADCs. The calibration takes care of both finite op-amp gain and capacitor mismatch. Unlike previous calibration techniques that use resistor ladder to generate the calibration signal, the proposed technique uses capacitors switching to reference voltages to eliminate the large RC time constants associated with...
This paper presents an ultra-low-power low-voltage Class-AB Fully Differential Operational Amplifier designed in 45-nm CMOS technology. The proposed circuit uses transistors operating in sub-threshold region for low-power and low-voltage operation. The proposed Op Amp offers an open-loop gain of 74.6 dB, 1 MHz unity gain frequency, 50-degrees Phase Margin, and 91.55 dB common-mode rejection ratio...
This paper presents a two stage low noise chopper amplifier for integrated angular acceleration sensor signal processing circuit which consists of amplifiers, phase-locked loop and automatic gain control. Capacitor feedback amplifier circuit is one of the most suitable for CMOS technology however capacitor amplifier with chopped op-amp has poor low frequency performance because of parasitic resistive...
In this paper, a low voltage fully differential neural amplifier based on current feedback operational amplifier (CFOA) is introduced. The gains of LFP and spikes signals can be tuned using the amplifiers capacitors. The designed amplifier provides a maximum output gain up to 50 dB, a total power consumption of 4.218 nW, and an input referred noise of 3.38 μV/Hz1/2 and 5.96 μV/Hz1/2 for LFP signals...
A frequency compensation technique for achieving high 3-dB bandwidth in two-stage operational amplifiers is demonstrated in this paper. Due to the phenomenon of pole splitting in Miller's Compensation technique in classical op-amp, the 3-dB bandwidth reduces drastically. The technique demonstrated in this paper is a modification of Miller's Compensation technique to achieve a significant improvement...
An auto-zero operational amplifier dedicated to space applications is proposed. Its operation principle is based on a continuous-time auto-zeroed amplifier topology to provide a low-level offset. The circuit was implemented in a standard 130 nm CMOS technology. Simulations show that the residual offset is reduced to a few microvolts. The gain bandwidth product is estimated at 10 MHz, and the slew-rate...
We report an 11-b 20-Ms/s pipelined ADC in 0.18-μm CMOS with a novel dual-mode-based digital background calibration method that altogether corrects errors caused by gain insufficiency, gain nonlinearity, and capacitor mismatches. The calibration enables an intentional use of low-gain single-stage op amps instead of conventional high-gain multi-stage op amps, with which we achieve a total ADC power...
We demonstrated the feasibility of the adaptive frequency compensation approach to design maximum- and constant-bandwidth feedback amplifiers. A basic CMOS amplifier exhibiting 66-dB dc gain and 310-MHz gain-bandwidth product was designed. For closed-loop gains ranging from 1 to 10, the closed loop bandwidth was found never lower than 401 MHz. A similar amplifier with equal gain-bandwidth product,...
Multistage operational amplifiers suitable for nanometer-scale CMOS technologies and low-voltage applications are described. The low intrinsic gain of transistors is compensated for with cascade of single-stage amplifiers. Techniques for compensations are revisited and the optimal solution identified. An example of a novel scheme that achieves 67 dB of DC gain, 320 MHz of bandwidth and 61 degrees...
This paper presents a high-speed CMOS OP Amp with a dynamic switching bias circuit capable of processing video signals of over 2 MHz with decreased dissipated power. The OP Amp, capable of operating at 10 MHz dynamic switching rate, was designed and showed through simulations a dissipated power of 66 % of that in conventional continuous operation. This OP Amp was applied to a switched capacitor (SC)...
This paper introduces electronically tunable voltage-mode and current-mode first-order all pass sections (APSs) employing operational trans-conductance amplifiers (OTAs) and grounded capacitor. The circuits can realize two all pass characteristics by choosing the current output of the OTA. Additionally, the circuit parameters ω0 and H can be set independently through adjusting the bias currents of...
This paper presents a new micro-power precision sample-and-hold (S/H) circuit for biomedical applications. In conjunction of low-power op-amp circuit design, the switched-capacitor capacitive-reset gain circuit with capacitor-mismatch compensation technique has been used. With this combination, the S/H has features of insensitive to capacitor mismatch, offset, and finite open-loop gain of op-amp whilst...
A gain modified CMOS Operational Transconductance Amplifier (OTA) for a 16 bit pipeline Analog-to-Digital Converter (ADC) is presented. The circuit is designed to be used for a high resolution and low sampling rate ADC. Gain boosting technique is implemented in the design to achieve high DC gain and settling time as required. Post layout simulations for a 5 pF load capacitance shows that OTA achieves...
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