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Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
This paper presents a low power continuous-time bandpass sigma delta modulator for analog to digital converter (ADC) over 5 MHz band. The modulator consists of a fourth order design operating at a Sampling Frequency of 280MHz. The operational transconductance amplifier (OTA) is linearized by using source degeneration technique. This paper investigates the effect of OTA linearization on the modulator...
In this paper a single full bridge resonant inverter with independent output power control of two cascaded loads for induction cooking application is presented. In proposed configuration, the full bridge inverter can be operated with constant switching frequency and constant duty ratio for efficient zero voltage switching. Independent output power control of each load is done by varying the duty ratio...
The work portrayed in this paper furnishes knowledge about advanced solar photovoltaic (PV) conversion system. This PV system is fast and tracks more output power than conventional PV systems. In literature, the PV parameters of a double exponential model were designed with the help of Levenberg-Marquardt algorithm. In this paper, the PV parametric values were taken into consideration and implemented...
In the current SoC implementation embedded memories are most widely used cores. They usually occupy a significant portion of the chip area, and dominate the manufacturing yield of the chip. Embedded memories have become very vulnerable to even minor process variations, resulting in low manufacturing yield & reliability. Efficient yield-enhancement techniques for embedded memories are thus important...
In this paper an analog to digital converter architecture is introduced. The proposed design is based on a mixed approach of flash type ADC and SAR type ADC. This design offers lesser number of comparators and so low power consumption with much less circuit complexity in comparison to conventional flash ADC architecture. Based on the proposed idea, a 4-bit ADC is simulated in Cadence virtuoso Tool...
The Ex-OR and Ex-NOR gates are the basic building blocks of various digital system applications like adder, comparator, and parity generator/checker and encryption processor. This paper proposes a full swing pass transistor based Ex-OR/Ex-NOR gate which gives better driving capability, less propagation delay and low power dissipation as compared to the existing Ex-ORlEx-NOR circuits, and by modifying...
In today's nanometric VLSI designs achieving both power and performance targets is the top most priority for design closure. Globally asynchronous locally synchronous (GALS) architectures can offer less dynamic power and improved performance due to absence of global clock. In GALS SoC architectures each synchronous blocks runs on their local clocks. Synchronous blocks communicate with each other by...
This paper presents a well-defined method for the design of a high gain, high CMRR two-stage CMOS operational amplifier using 0.18μm CMOS technology for Bio-medical applications. The Op-amp consists of a cascade of Folded-cascode differential amplifier in first stage followed by a fully differential amplifier with PMOS current source load in second stage. The gm/Id technique is employed in designing...
This paper presents a design methodology using multiplexers to implement any ternary logic function with carbon nanotube field effect transistors (CNFETs). Ternary logic is one of the promising alternatives to conventional binary logic, since it is possible to achieve simplicity and low power dissipation due to the reduced circuit such as interconnects and chip area. The paper presents a design methodology...
Today's Power system is more complex and consequently it would lead to less security. To meet the demand and better security levels with existing transmission lines, the Flexible AC Transmission System (FACTS) devices are one of the alternates. In this paper a Newton Raphson(NR) algorithm was developed to find out the best operating point of a Static Var Compensator(SVC) for the enhancement of system...
Here, we report high voltage MOSFET modeling using BSIM6 model. The model has two components — intrinsic MOSFET channel of LDMOS modeled by BSIM6 and a drift region modeled by non-linear drift resistance. BSIM6 is the next generation bulk MOSFET model in BSIM family of models. It also have the model of Self Heating Effect (SHE) which is very important for high power devices like LDMOS. This model...
Cascaded multilevel inverters synthesize a medium-voltage output based on a series connection of power cells which use standard low-voltage component configurations. This characteristic allows one to achieve high-quality output voltages and input currents and also outstanding availability due to their intrinsic component redundancy. Due to these features, the cascaded multilevel inverter has been...
Assistive robotics will help the physically disabled persons in many ways. They attempt to restore human abilities that have been reduced or lost by disease, accident, or old age. In this paper we described about how the P300 based Brain Computer Interface (BCI) system controller will work and employed to improve the conventional controlling methods by interpreting the normal BCI system with path...
One of the key challenges in micro scale energy harvesting system is that the output voltages produced by the tiny transducers are very low (0–0.4V). Therefore a charge pump(CP) with high voltage step up ratio is essential to boost the voltage, and charge an energy buffer for storage. Conventional Linear and Fibonacci charge pumps have better current driving capabilities at higher and lower voltage...
Single ended data sensing for asymmetrical low voltage memories has become a topic of much interest due to its application in very low energy computing and communication. In this paper, we present an ultra-high-speed (UHS) data sensing scheme for single ended near threshold asymmetric static random access memory (SRAM) design in a 45nm standard CMOS process. The proposed bit-line decoupled single...
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