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Programmable devices such as SRAM-based FPGAs have the major challenges of power consumption and circuit area due to the excessive standby leakage current and the threshold voltage variation in highly scaled SRAM. Back-end-of-line (BEOL) device, which is integrated in the interconnect layers, is attractive for reducing the performance gap between FPGA and cell-based ASIC. In this paper, we demonstrate...
Due to direct impact on power supply and thermal component selection, power consideration within the system power budget and operation environment is becoming increasingly important. In this paper, it analyses the sources of FPGA power consumption, present situation, design consideration, popular technologies and analysis tools, etc. It will give readers a general understanding of power consumption...
Quaternary logic has shown to be a promising alternative for implementing FPGAs, since voltage mode quaternary circuits can reduce the circuits' cost and at the same time reduce its power consumption. In this paper, we study the implementation of circuits in quaternary logic. To obtain cost-effective implementations of quaternary circuits, we propose a mapping from binary to quaternary circuits based...
Interconnections play a crucial role in todays deep sub-micron designs because they dominate the delay, power and area. This is especially critical for modern million-gates FPGAs, where as much as 90% of chip area is devoted to interconnections. Multiple-valued logic allows for the reduction of the required number of signals in the circuit, hence can serve as a means to effectively curtail the impact...
Energy-performance tunable circuits enable the user to adjust the energy and performance of a chip after fabrication to suite the particular application, thus increase the overall power efficiency of the chip. Two tunable interconnect architectures are proposed. Pseudo-static interconnect achieves the same performance as static interconnect while consuming only 65% as much energy and provides 2X wider...
This paper describes the integration of a thermally assisted switching magnetic random access memory (TAS-MRAM) in FPGA design. The non-volatility of the latter is achieved through the use of magnetic tunneling junctions (MTJ) in the MRAM cell. A thermally assisted switching scheme is used to write data in the MTJ device, which helps to reduce power consumption during write operation in comparison...
The increased flexibility offered by FPGAs implies that more transistors are needed which leads to higher power consumption per logic gate. FPGAs power consumption is fast becoming an essential design consideration especially for mobile systems with a limited power supply. The effect of components' region-constrained placement on reducing internal nets total capacitance and the corresponding change...
The increased flexibility offered by FPGAs implies that more transistors are needed which leads to higher power consumption per logic gate. FPGAs power consumption is fast becoming an essential design consideration especially for mobile systems with a limited power supply. The effect of components' region-constrained placement on reducing internal nets total capacitance and the corresponding change...
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