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We describe the fabrication of radiation dosimeters utilizing fully-depleted silicon-on insulator (FDSOI) substrates, and further demonstrate the detection of various ionizing radiation types including protons, a-particles, and X-rays by the threshold voltage (Vth) changes caused by the radiation-induced charge trapped in the buried oxide. Our FDSOI dosimeter exhibits a sensitivity of ~3 mV/krad(SiO...
We hereby present for the first time a successful Dual Strained Channel On Insulator (DSCOI) planar co-integration of tensily strained SOI nFETs and compressively strained SiGe pFETs down to 17nm gate length with functional ring oscillators and 6T SRAM cells. Various Ge contents and growth templates (unstrained or strained SOI) were screened in order to optimize the trade-off between threshold voltage...
In this paper, the characteristics of static random access memory (SRAM) cells based on three silicon-on-insulator (SOI) device structures are studied using device simulations. The comparative study, which is performed in a 32nm standard CMOS technology, includes read static noise margin (read SNM), read current, and standby power. The structures include SOI with ground plane in substrate (SOI-GPS),...
Partially depleted (PD) SOI CMOS technology has advanced from a small radiation hard niche market in the past to present main stream commercial applications because of advantages relative to device isolation and single event upset mitigation [1]. This paper is to investigate and present how the core 45nm SOI devices would behave in the total dose ionizing dose (TID) environment using a laboratory...
We report an original Dual Channel-On-Insulator (DCOI) Fully Depleted CMOS architecture by co-integrating nFETs on sSOI and pFETs on Si/SiGe/(s)SOI with a TiN/HfO2 gate stack (EOT=1.15 nm) and down to 40 nm gate lengths. We demonstrate for the first time large gains for transconductance (up to +125%) and mobility (+100%) even for short channel pFETs. This enables us to improve the ON(OFF) pFETs trade-off...
The authors explored some of the challenges of the extremely thin SOI technology for mainstream CMOS. Faceted RSD was used to minimize parasitic capacitance. PFET performance is competitive with best bulk CMOS technologies, while NFET performance can be increased by further reduction in the series resistance. The impact of silicon thickness on the device variability was studied to quantify wafer uniformity...
The minimum operating voltage, Vmin, of memory-rich nanoscale CMOS LSIs is investigated to open the door to the below 0.5-V era. A new method using a timing margin is proposed to evaluate Vmin. It shows that Vmin is very sensitive to the threshold-voltage variations, ΔVt, which become more significant with device scaling, and to the lowest necessary threshold voltage, Vt0, of MOSFETs. As a result...
This paper demonstrates the effectiveness and advantages of ULP (Ultra-Low-Power) MOS diodes vs. standard implementations of a AC-DC voltage multipler in a 150nm multiple-threshold voltage SOI CMOS technology for RFID applications. Introducing a specific design methodology, we compare two 3 stages voltage multipliers, each using one of those diodes types and driving a 1.5??A load. Both architectures...
Recently, minimizing the standby power is considered as a critical issue in high-density, mobile CMOS technology. One of the major sources of the leakage current in off-state of ultra-small MOSFET is gate-induced drain leakage (GIDL) which is mainly composed of inter-band and trap-assisted tunneling. By virtues of reduced intra-junction and punch-through leakage currents, threshold voltage controllability,...
To enable medical implants such as artificial retina, smart stent microsensors and other implantable wireless sensors, we developed a biocompatible and flexible RF CMOS technology based on a 0.18 mum CMOS process on 8-inch SOI (silicon on insulator) wafers. The silicon substrate for MOS transistors is 1 mum thick and sandwiched between two parylene layers. Since the potential implantable microsystems...
Sub-40 nm Lgate asymmetric halo and source/drain extension transistors have been integrated into leading-edge 65 nm and 45 nm PD-SOI CMOS technologies. With optimization, the asymmetric NMOS and PMOS saturation drive currents improve up to 12% and 10%, respectively, resulting in performance at 1.0 V and 100 nA/mum IOFF of NIDSAT=1354 muA/mum and PIDSAT=857 muA/mum. Product-level implementation of...
Off-state leakage current in a 65 nm partially depleted (PD) floating-body (FB) SOI technology is modeled and analyzed with emphasis on its drain-voltage dependence. Modeling accuracy of the off-state leakage current is highly dependent on modeling of parasitic currents, although their direct contribution to the leakage may be negligible in lower-power/high-performance technologies. The underlying...
In this paper, a TCAD-based simulation study on lithography process-induced gate length variations has been performed. This study aims at evaluating fully depleted silicon on insulator (FD SOI) MOSFETs for next generation CMOS devices. Critical dimensions (CDs) have been obtained using rigorous lithography simulations. The impact of the resulting gate length variations on the electrical behavior of...
This paper introduces a novel voltage sense amplifier (VSA) in fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. Three different architectures are described and their operation margins are analyzed as a function of transistor length (L) and threshold voltage (Vth) variations and mismatch. The proposed architecture takes advantage...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
We present a predictive three interfaces coupling model in long channel Ultra Thin Body SOI MOSFETs. This model includes the effects of volume inversion, thin BOX and film, and substrate-BOX interface. This allows us to perfectly reproduce both simulations and experimental results extracted on FDSOI nMOSFET with 145 and 11 nm thick BOX.
Device optimization on partially-depleted silicon-on-insulator (PD-SOI) CMOS is systematically performed in terms of circuit switching speed and power consumption. The effects of several key factors, such as threshold voltage (Vth), pre-amorphization implantation (PAI), and silicon film thickness (Tsi), are fully investigated and optimized to achieve optimal ring-oscillator performance. We found that...
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