The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Since integration drives wireless business in order to achieve the appropriate cost and form factor, we see significant research concerning front end module (FEM) integration on silicon. In this quest, SOI technology has emerged as the technology of choice since the antenna switch and the power amplifier (PA) have been successfully integrated on SOI. In this paper, we will focus our investigation...
A production released complementary-SiGe BiCMOS technology on SOI has been developed for high speed analog and RFIC applications. It features matched SiGe:C PNP and NPN transistors. The PNP shows cutting edge performance metrics with β·VA = 17,000 and near record fT·BVCEO ≥ 195GHz·V for a 5V process while demonstrating best in class linearity on a fully differential amplifier design. A modular process...
A class E power amplifier (PA) has been designed and simulated for multi-radio applications in the 1.8 to 5GHz frequency band using a 130 nm CMOS-SOI technology. The PA is a single stage, single ended, self-biased cascode formed by a thin oxide transistor as common source device and a laterally diffused MOS (LDMOS) transistor as common gate. Switched fully integrated high current inductors are used...
A single-pole double-throw novel switch device in 0.18 ??m SOI complementary metal-oxide semiconductor (CMOS) process is developed for 0.9 Ghz wireless GSM systems. The layout of the device is optimized keeping in mind the parameters of interest for the RF switch. A subcircuit model, with the standard surface potential (PSP) model as the intrinsic FET model along with the parasitic elements is built...
Silicon-on-sapphire (SOS) was invented in 1961 and as such is the first of the SOI technologies. Its original purpose was to provide radiation tolerant circuits for satellites and missiles. Now, SOS is ready to displace gallium arsenide (GaAs) as the technology of choice for RF communications in commercial applications. What are the reasons for this? In this paper, I will share what we have learned...
During past years, high resistivity (HR) SOI CMOS technology has emerged as a promising one for the integration of RF applications, mainly because of the improvement of passive component related to HR substrate. In this trend, 3D symmetrical inductor (3DSI) has been proposed on SOI to lower the amount of area consumed by inductor while offering comparable performances than equivalent bulk technology...
We describe a 0.18/0.5 um RF CMOS thick Silicon-On-Insulator (SOI) technology built on high resistivity (1 kOhm-cm) substrates. A high performance/high power RF MEMS contact switch can also be integrated in the technology through above-IC post-processing. This RFCMOS/MEMS integrated technology provides a platform for cost-effective monolithic integration of several RF RX/TX functions for next generation...
The effects of 63 MeV proton irradiation on 65nm Silicon-On-Insulator (SOI) CMOS technology are presented for the first time. The radiation response of the CMOS devices was investigated up to an equivalent total gamma dose of 4.1 Mrad (SiO2). We analyze the implications of proton irradiation on RF performance of these devices. The cut-off frequency is degraded due to post-irradiation degradation of...
This paper discusses the design of a 60 GHz low noise amplifier (LNA) using a standard low power SOI CMOS process from ST Microelectronics. First, we outline the technology as well as the mm-wave design challenges. Using recent work on coplanar waveguide (CPW) modeling, we describe how it's possible to use parametric, 3D electromagnetic simulation to complete or replace analytical models of on-chip...
Scaling of CMOS transistors beyond 45 nm requires architectural redesign of the devices. FinFETs are proposed to recover the reduced channel control. This work evaluates the perspective of RF design in planar bulk vs. FinFET SOI for (sub-)45 nm CMOS on a key RF circuit: a low-noise amplifier (LNA). The planar and FinFET devices with channel lengths down to 40 nm are compared in both wideband and narrowband...
In this paper we present the results of several key circuit blocks such as amplifiers, mixers and an oscillator in a 90 nm SOI CMOS technology. The circuits were optimized for low noise. Leading-edge results such as 3.8 dB noise figure (NF) up to 40 GHz and more than 8 dB gain up to 60 GHz for a wideband amplifier, a low loss of only 4.8 dB for a drain pumped transconductance mixer at 35 GHz consuming...
To enable the wide deployment of ambient intelligence, where various environmental parameters can be sensed and reported, the main challenge consists in developing low-cost, low-power and miniaturized sensor tags composed of an integrated circuit, a sensor and an antenna. Sensor tags are also of great interest for healthcare applications, such as blood or air pressure measurement in Renard, S., et...
We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fT's of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The...
This paper presents high-Q and high-inductance-density on-chip inductors made on high resistivity (HR) substrate using STMicroelectronics LP 65 nm SOI CMOS technology with 6 copper metal layers. For the first time, on-chip inductor architectures dedicated to HR SOI CMOS technology are reported and benchmarked with current one used in standard RF CMOS technologies. According to the measurement results,...
We report on an implementation of a self-powered radio-frequency identification tag in a three-dimensional silicon on insulator (3D SOI) process, which uses backscatter modulation to send a hardwired digital code to a scanner.
An ultra-small RFID chip uses an electron beam for writing 1T memory cells. A 90nm SOI CMOS process and double-surface electrode chip structures enable the design of 0.05times0.05mm2 and 5mum-thick RFID chips with small, low-cost and highly-reliable 128b ID-memory. The chip is verified at a carrier frequency of 2.45GHz with measured communication distance of 300mm.
Ultra-small radio frequency identification (RFID) chip with its antenna technology is described. The key techniques used in this ultra-small chip to reduce chip size and cost are embedded antenna, double-surface electrode and silicon on insulator (SOI).
A 0.15times0.15mm2 RFID chip containing a 128b ROM is fabricated in a 0.18mum 4M SOI CMOS technology. It achieves 480mm read range with a 2.45GHz carrier for a reader output power of 300mW. The chip is thinned precisely by using an SOI buried oxide layer structure as an etch stop. An RFID antenna is connected to the chip by using a double-surface electrode
This paper describes the experimental characteristics of RF components with layout and structural optimization, fabricated in 0.10-mum 1.2-V SOI-CMOS technology with partial trench isolation (PTI). ESD protection-grounded gate SOI-NMOSFETs achieve high reliability due to body-tied structure with PTI, and newly proposed ESD diodes also derive superior performance. Moreover, this technology offers a...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.