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A 1/2.7 inch 1944times1092pixels CMOS image sensor with multi-gain column amplifier and double noise canceller is fabricated in a 0.18mum 1P3M CMOS process. It operates at 48MHz in a progressive scanning mode at 60fps. A 2T/pixel architecture and low optical stack with micro innerlens achieve 14.8ke-/1x-s sensitivity, 14ke- saturation, 3.7e-rms noise and 12.2e- dark current at 60degC.
A DLL featuring jitter-reduction techniques for a noisy environment is described. Loop behavior is controlled by monitoring the amount of jitter caused by supply noise of a replica delay line. The DLL is implemented in a 0.13mum CMOS process, and at 1 GHz, it has 4.58psrms jitter and 29pspp jitter with noisy replica delay line.
A 512kb SRAM module is implemented in a 45nm low-standby-power CMOS with variation-tolerant assist circuits against process and temperature. A passive resistance is introduced to the read assist circuit and a divided VDD line is adopted in the memory array to assist the write. Two SRAM cells with areas of 0.245mum2 and 0.327mum2 are fabricated. Measurements show that the SNM exceeds 120mV and the...
An interface ASIC for a capacitive 3-axis micro-accelerometer is implemented in a 0.13μm CMOS process. Die area and power dissipation are reduced by using time-multiplexed sampling and duty cycles down to 0.3%. The chip with 0.51 mm2 active area draws 62μA from a 1.8V supply while sampling 4 proof masses, each at 1 kS/s. With a plusmn4g capacitive 3-axis accelerometer, the measured noise in the x,...
An all-digital UWB TX is presented that generates PPM pulses with a center frequency tunable to 3 channels in the 3.1-to-5GHz band without the use of an RF oscillator. A delay-based spectral scrambling technique is proposed that exploits the digital architecture. The circuit achieves 47pJ/b at a data rate of 10Mb/s.
A dual-band transceiver able to work on both UWB low band (3 to 5GHz) and high band (7 to 9GHz) is presented. A method of DSB upconversion in TX, and SSB downconversion and detection in RX is proposed to achieve high data rate non-coherent communication. Realized in 0.18 mum CMOS, the RX achieves an NF of 9.4dB, an IIP3 of -10.3dBm, and a sensitivity of -76dBm. It can attain a transmission rate up...
A fully integrated 24GHz 4-channel phased-array transceiver in 0.13μm CMOS is reported. The architecture is based on a variable-phase ring oscillator in a PLL that modulates the baseband for each antenna in the TX mode and downconverts the received signal from all antennas in the RX mode without using RF mixers, signal-path phase shifters, or any power combining network. The 2.3 × 2.1 mm2 chip achieves...
A UWB transceiver in baseline 65nm CMOS is presented. The chip has an active area of 0.4mm2 and draws 95mA from a 1.2V supply. It achieves a NF between 5 and 5.5dB over a 3 to 8GHz bandwidth and targets MB-OFDM UWB band groups 1 and 3. The IIP3 of +5dBm and II2 of +24dBm make the design suitable for applications where interferer-robust operation is important.
A 33.6-to-33.8 Gb/s burst-mode CDR circuit is realized in 90nm CMOS technology. The LC gated VCO, the phase selector the input matching circuit, and the wideband data buffer are discussed. With 2n-1 PRBS input, the measured rms jitter for the recovered data is 1.15ps at 33.72Gb/s. This CDR can tolerate 31 consecutive identical bits with a locking time of 0.2ns (<7b interval). It consumes 73mW from...
The design and experimental verification of a 20Gb/s CDR circuit based on injection-locking technique is presented. Fabricated in 90nm CMOS technology, this circuit achieves a BER of <10-9 for both continuous and burst modes. It has tunability of over 800Mb/s while consuming 175mW. The re-acquisition time of this CDR is 1b interval.
A 4-wavelength DWDM optoelectronic transceiver, implemented in a 0.13mum CMOS SOI process, achieves an aggregate rate of 40Gb/s transmission over single fiber. The four channel WDM chip, operating all four Txs and Rxs in WDM configuration consumes -3.5W. This is at nominal operating conditions.
A static CML divide-by-2 frequency divider is integrated in 65nm SOI CMOS. The maximum operating frequency is 90GHz while dissipating 52.4mW. The self-oscillation frequency is 92GHz with 0.57pJ switching energy. Measurement of self-oscillation frequency at multiple bias conditions enables estimation of the variation in threshold voltage, capacitance, and resistance.
A 512Mb diode-switch PRAM is developed in a 90nm CMOS technology. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described. Through these schemes, the PRAM achieves read throughput of 266MB/S and maximum write throughput of 4.64MB/S with a 1.8V supply.
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