The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Peridynamic (PD) theory is used to investigate the dynamic responses of electronic packages subjected to impact loading arising from drop-shock. The capability of the PD theory to predict failure is demonstrated by simulating a drop test experiment of a laboratory-type package. The failure predictions and observations are exceptionally similar. For the drop test simulation of a production-type package,...
3D packaging is one of the main emerging markets especially for mobile application within the last view years. Mobile devices are exposed and hence need to be reliable under to vibration or mechanical shock conditions. Therefore, material properties covering strain rate dependency have to be at hand within reliability studies. Miniature bulk specimens were utilized to gain stress and strain data at...
Thus far, there is a severe lack of understanding about interfacial fracture and impact behavior of the microscale lead-free solder interconnects. In this study, the finite element simulation and analytical method were used to characterize the interfacial fracture and impact behavior at the interfaces of the microscale Sn-Ag-Cu solder joints. The intersection of a linear microcrack tip upon Sn-Ag-Cu...
Wafer level Chip Scale Package (WLCSP) fulfills the demand for small, light, and portable handheld electronic devices, and it is one of the most advanced packaging concepts. When the WLCSP was assembled on board level, the connection, i.e. solder joints are generally the critical and challenging issue for the whole device's reliability. In addition to the shape and material of solder joints, the material...
Interfacial fracturing is the most important failure mode of solder joints. In this paper, interfacial stresses of Cu pad/solder interfaces are evaluated based on the theory of interfacial mechanics and the finite element method. Effects of solder joint shapes and solder materials on the stress intensity are investigated. The results show that Sn37Pb/Cu interface has greater stress intensity than...
In this paper, the investigation focuses on the copper stud bump solder joint thermal-mechanical reliability. The copper stud bump processing is simulated by FEM software Ansys/Ls-dyna, and then the relationship between the copper stud bump and processing parameters (bonding force, ultrasonic power, bonding time and bonding temperature) is studied. Based on the simulation result, the dimension of...
The interface damage of single solder joint was simulated using cohesive zone model incorporated in finite element analysis. In this study, the solder/IMC/Cu pad interfaces models were constructed for the molecular dynamics simulation. The traction-separation law was derived when the interface model was subjected to a principle strain in one direction. The materials properties of cohesive element...
There is a significant need for next-generation, highperformance power electronic packages and systems with wide band gap devices that operate at high temperatures in automotive and electric grid applications. Sn-3.5Ag solder is a candidate for use in such packages with potential operating temperatures up to 200°C. However, there is a need to understand thermal cycling reliability of Sn-3.5Ag solders...
This study addresses the mechanics of the relatively brittle solder/intermetallic (IMC) interface fracture process using damage mechanics concept. The damage state, ?? of a material point in the solder/IMC interface, is expressed in terms of orthogonal traction components in a quadratic failure criterion of a cohesive zone model. The model is then employed in a finite element analysis of a solder...
BGAs packaging offer high pin counts and lower interconnecting space, and are suitable for high density packaging. However, it is difficult to inspect individual solder joints on BGA assembly by conventional visual methods and need a complicated practice on rework. Ball impact test is a useful method to estimate the reliability of BGA solder joint. In this study, the three-dimensional explicit finite...
An array of accelerated temperature cycling (ATC) finite element (FE) simulations using ANSYStrade, and drop-impact finite element simulations using LS DYNAtrade, are used to find the optimum elastic modulus and coefficient of thermal expansion (CTE) for a stacked chip scale package. For the ATC simulations, Anand's constitutive model with properties for Sn96.5Ag3.0Cu0.5 (SAC305) and tin-lead eutectic...
The effect of thinning down the chip thickness, will affect the stress pattern in the chip and causes the chip to deform locally when the thickness of the chip is thinner than a certain critical value. Such a local deformation may cause sharp gradient of residual stress around the solder bumps and thus, various failures. This paper shows that by considering the effect of solder bumps on a 50 mum chip,...
Copper/Low-k structures are the desired choice for advanced integrated circuits (ICs) as the IC technology trends moving toward finer pitch, higher speed, increased integration and higher performance ICs. Copper interconnects with low-k dielectric material improves the ICs performance by reducing interconnect RC delay, cross talk between adjacent metal lines and power loss. However, low-k materials...
The technique of wafer level chip scale package (WLCSP) is similar as flip chip packages without using underfill. The weakest point is solder joint reliability issue so the package size of WLCSP in current industry is used less than 10times10 mm2. In this paper, we use 5.5times5.5 mm2 package size to take as test vehicle and focus on ball peeling and shear stresses to assume and simulate drop test...
Due to the smaller size of HDD, fault deformation of solder bumps is found more often. In order to study about a factor relating to fault deformation of solder bumps, the FEM is used to investigate stress performance. The results show that a small number of bumps positioned in a symmetric form have similar stress while a small number of bumps positioned in the asymmetric form have different stress...
A thermodynamics-based damage mechanics rate dependent constitutive model is used to simulate experiments conducted on thin layer eutectic SnAgCu(SAC) solder joints. The non-damage constitutive is measured by bulk tensile test. The relationship between true stress and strain is sigma=85.26epsiv0.3536. Damage evolution equation is proposed based Lemaitre ductile damage theory and the constant in the...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.