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Modern FPGAs, due to its many advanced features, have become a popular implementation platform for various applications like aerospace, defence, automotive, cryptography and many more. Additionally, modern FPGAs are equipped with high performance hard-IPs which has reduced the performance gap between ASIC and FPGAs significantly. Dynamically Reconfigurable Look-up-Tables (RLUT) is an advanced feature...
Field Programmable Gate Arrays (FPGAs) are being increasingly deployed in diverse applications including the emerging Internet of Things (IoT), biomedical, and automotive systems. However, security of the FPGA configuration file (i.e. bitstream), especially during in-field reconfiguration, as well as effective safeguards against unauthorized tampering and piracy during operation, are notably lacking...
AES is the predominant block cipher used worldwide in many cryptographic applications. Despite of the wealth of already available implementations, we here introduce an ultra-lightweight AES-128 implementation specifically tailored for reconfigurable hardware. Our basic proposal presents a full AES-128 providing 9.12 Mbit/s throughput and occupying just 21 slices of a Spartan-6 and no additional memories...
This paper present method for constructions of the S-Box for Advanced Encryption Standard (AES) algorithm using composite field arithmetic in GF(((22)2)2). It is advantageous to implement the composite field arithmetic (CFA) on Field Programmable Gate Array for AES algorithm. Moreover, architectural implementation of S-Box using CFA reduces the hardware in terms of gates count as compared with that...
Advanced Encryption Standard (AES) is a symmetric cryptographic algorithm used for protecting data. Designing efficient hardware architecture for AES with small hardware resource usage is a challenge. AES uses different data transformations and the most expensive one, in terms of computational resources, is the SubBytes transformation which is carried out by a Look-Up-Table (LUT) named the S-box....
Reconfigurability is a unique feature of modern FPGA devices to load hardware circuits just on demand. This also implies that a completely different set of circuits might operate at the exact same location of the FPGA at different time slots, making it difficult for an external observer or attacker to predict what will happen at what time. In this work we present and evaluate a novel hardware implementation...
While advanced encryption standard (AES) is extensively in use in a number of applications, its area cost limits its deployment in resource constrained platforms. In this letter, we have implemented SIMON, a recent promising low-cost alternative of AES on reconfigurable platforms. The Feistel network, the construction of the round function and the key generation of SIMON, enables bit-serial hardware...
This paper proposes an efficient method for implementing parallel AES-GCM cores using FPGAs. The proposed method improves the performance of the parallel architecture (Throughput/Slice). Presented architectures can be used for applications which require encryption and authentication with slow changing keys like Virtual Private Networks (VPNs). Our architectures were evaluated using Virtex5 FPGAs....
Hardware implementation provides a higher level of security and cryptography speed at some lower resource cost, compared to software implementation of AES. In this paper, we present a balanced hardware design and implementation for AES, considering several existing implementations. FPGA implementation offers higher speed solution and can be easily adapted to protocol changes, although the AES can...
This paper proposes a rolled architecture for the implementation of the 128 bit AES (Advanced Encryption Standard) algorithm. The design comprises of modified T-boxes. The efficient utilization of area and the increase in speed up to 1.454 Gbps is achieved on Xilinx's Virtex-4 Field Programmable Gate Array (FPGA). The clock frequency of the design is 113.63 MHz. By using 24 bit words instead of 32...
Self-healing systems can restore their original functionality by use of run-time self-reconfiguration, a feature supplied by state of the art FPGA devices. Commonly, integrity checks are performed by reading back the device configuration and validating its hash value. Systems which are prone to tampering and piracy of intellectual property may disable configuration readback, which renders this method...
In this paper, compact architectures for AES Mix Column and its inverse is presented to reduce the area cost in resulting AES implementation. In the hardware implementation of AES with direct mapping substitute byte optimization, MixColumn/Inverse MixColumn transformation demands the utilization of logic resources and then effects the critical path delay and resulting throughput. The proposed MixColumn/Inverse...
Many applications require protection of secret or sensitive information, from sensor nodes and embedded applications to large distributed systems. The confidentiality of data can be protected by encryption using symmetric-key ciphers, and the integrity of the data can be ensured by using a cryptographic hash function to calculate a "digital fingerprint." In this paper, we propose reconfigurable...
Hummingbird is a new ultra-lightweight cryptographic algorithm targeted for resource-constrained devices like RFID tags, smart cards, and wireless sensor nodes. In this paper, we describe efficient hardware implementations of a stand-alone Hummingbird component in field-programmable gate array (FPGA) devices. We implement an encryption only core and an encryption/decryption core on the low-cost Xilinx...
The NTRU encryption algorithm, also known as NTRUEncrypt, is a parameterized family of lattice-based public key cryptosystems. Both the encryption and decryption operations in NTRU are based on simple polynomial multiplication which makes it very fast compared to other alternatives such as RSA, and elliptic-curve-based systems. Recently, the NTRU system has been accepted to the IEEE P1363 standards...
This paper describes the field programmable gate array (FPGA) implementation of Rijndael algorithm based on a novel design of S-box built using reduced residue of prime numbers. The objective is to present an efficient hardware implementation of Rijndael using very high speed integrated circuit hardware description language (VHDL). The novel S-box look up table (LUT) entries forms a set of reduced...
The article presents a pipeline implementation of the block cipher CLEFIA. The article examines three known methods of implementing a single encryption round and proposes a new fourth method. The article proposes the implementation of a key scheduler, which is highly compatible with pipeline encryption. The article contains a detailed analysis of the data processing path for the 128-bit key version...
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