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A recent trend in the electronics industry is the concept of intelligent wearables and the Internet of Things (IoT) such as smart watches, fitness trackers, smart sensors, and smart glasses. Low power consumption is a requirement of the processors and the increasingly large embedded SRAMs in such devices. Lowering the operating voltage of these devices makes them low power. However, process variation...
ReRAM (Resistive Random Access Memory) is an emerging non-volatile memory technology that exhibits high cell density and low standby power. ReRAM crossbars, while having the smallest 4F2 cell size, suffer from large sneak leakage, which not only wastes dynamic energy but also degrades system performance significantly. In this paper, we propose V-ReRAM, a novel ReRAM crossbar design based on 1TnR cell...
Spin-transfer torque magnetic RAM (STT-MRAM) is one of the most promising nonvolatile memories with guaranteed high-speed read and write operations. Along with performance improvements in the tunnel magnetoresistance (TMR) and the magnetic tunnel junction's (MTJ) required switching current, there have also been reports on high-capacity (up to tens of Mb) STT-MRAM [1–4]. In [2] a perpendicular-TMR...
For the design and verification of a heterogeneous system architecture containing analog, digital, and software functionality, the use of modern languages and advanced Electronic System-Level (ESL) top-down design methodologies becomes fundamental. This paper will present the industrial application of the SystemC analog/mixed-signal (AMS) extensions in combination with SystemC and other C++ libraries,...
Resistive random access memories (RRAMs)have arisen as a competitive candidate for non-volatile memories due to their scalability, simple structure, fast switching speed and compatibility with conventional back-end processes. The stochastic switching mechanism and intrinsic variability of RRAMs will poses challenges that must be overcome prior to their massive memory commercialization. However, these...
Read access in STT-MRAMs is well known to be highly sensitive to process variations. Such variations are responsible for read bit error rates that are worse than conventional CMOS memories (e.g., SRAM) by orders of magnitude, especially at low voltages. In this work we propose a boosted sensing scheme to improve the resiliency of STT-MRAM against variations in read accesses based on the voltage sensing...
In this paper, we propose the integration of an Al2O3/CuTex based Conductive Bridge RAM (CBRAM) device in vertical configuration. The performances of the memory devices are evaluated. 20ns switching time, up to 106 cycles and stable 150°C retention were demonstrated. Functionality is compared with Vertical RRAM integrating an HfO2/Ti OXRAM stack, showing the pros and cons of each configuration. Then...
Spin Torque Transfer RAM (STT-RAM), a assuring possible choice of Static RAM for diminishing leakage power utilization. STT-RAM has the resistance of the MTJ (Magnetic Tunnel Junction) that changes based on stored data. By using differential sensing with reconfigurable cache cell, the STT-RAM performance can be improved. This scheme largely reduces the read disturbance error and average power dissipation...
Spin-transfer torque random access memory (STT-RAM) recently received significant attentions for its promising characteristics in cache and memory applications. As an early-stage modeling tool, NVSim has been widely adopted for simulations of emerging nonvolatile memory technologies in computer architecture research, including STT-RAM, ReRAM, PCM, etc. In this work, we introduce a new member of NVSim...
We describe a methodology to model the low power and voltage behavior of multi-voltage custom memories in processors. These models facilitate early power-aware verification by abstracting the transistor-level representation of the memory to its power-aware behavioral RTL model. To the best of our knowledge, this is the first attempt at addressing the power-aware RTL model generation problem for custom...
Several memory vendors are pursuing different kinds of memory cells that can offer high density, non-volatility, high performance, and high endurance. There are several on-going efforts to architect main memory systems with these new NVMs that can compete with traditional DRAM systems. Each NVM has peculiarities that require new microarchitectures and protocols for memory access. In this work, we...
A circuit technique based on hardware replication improves the robustness of the FPGA circuitry against dynamic and/or static power attacks. Due to its nMOS-MUX based structure, the proposed circuit also exhibits an increased robustness against early evaluation attacks and those based on glitches. The secured LUT and switch are 3.4× and 1.5× larger than their standard counterparts, respectively. Given...
Memristor's on/off resistance can naturally store binary bits for non-volatile memories. In this work, we found that memristor's another peculiar feature that the switching takes place with a time delay (we name it "the delayed switching") can be used to selectively address any desired memory cell in a crossbar array. The analysis shows this is a must-be in a memristor with a piecewise-linear...
Whereas buffers significantly impact Network-on-Chip (NoC) performance, they also account for up to 75% and nearly 50% of NoC router area and power respectively. Traditionally, SRAM has been used as an area and power efficient implementation of the router buffer. However, motivated by the smaller size and lower-power potential of planar embedded DRAM (eDRAM), we implement the router buffer using a...
Conventional spin-transfer torque random access memory (STT-RAM) is a promising technology due to its non-volatility and dense cell structure. However, the long switching time of magnetic tunneling junction (MTJ) limits the write speed of the STT-RAM. In order to improve the write performance, a Spin-Hall Effect (SHE) assisted STT-RAM structure (SHE-RAM) has recently been proposed [1]. SHE effect...
We present an ultra-low-power Microcontroller Unit (MCU) with an embedded atom switch ROM, which performs a 0.33–1.2 V operation voltage and 46.8-µA/MHz active current (or 18.26-µW/MHz active power). The MCU is fabricated by the hybrid of Silicon-On-Thin-Buried-oxide (SOTB) CMOS and bulk CMOS [1]. The SOTB CMOS with a body-bias voltage control realizes a high drivability up to 40-MHz operation at...
In the last decade, academies and private companies have actively explored emerging memory technologies. STT-MRAM in particular is experiencing a rapid development but it is facing several challenges in terms of performance and reliability. Several techniques at cell level have been proposed to mitigate such issues but currently few tools and methodologies exist to support designers in evaluating...
A deeper understanding of the impact of variability on Oxide-based Resistive Random Access Memory (so-called OxRRAM) is needed to propose variability tolerant designs to ensure the robustness of the technology. Although research has taken steps to resolve this issue, variability remains an important characteristic for OxRRAMs. In this paper, impact of variability on OxRRAM circuit performances is...
In recent researches, much emphasis has been placed in developing non-volatile memories as candidates for replacement of volatile memories. Apart from non-volatility, memristive devices also have high switching speed, low energy consumption, and small device size. In this article, a novel one-bit memory cell using two transmission gates and one memristor (2TG1M) is proposed. SPICE simulations were...
The design of a commercially-shipping 72-port 10G Ethernet switch router integrated circuit is presented. The 1.2 billion transistor chip consists of a core of > 1GHz asynchronous circuits surrounded by standard synchronous logic for external interfaces. It is manufactured in a TSMC 65nm process. The asynchronous circuitry includes 15MB of single-ported SRAM, 150KB of dual-ported SRAM, 100KB of...
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