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Three different methods for the extraction of the contact resistance based on both the well-known transfer length method (TLM) and two variants of the Y-function method have been applied to simulation and experimental data of CNTFETs and the results have been compared. While for TLM special CNT test structures are mandatory, standard electrical device characteristics are sufficient for the Y-function...
Quasi-ballistic electron transport in ultrashort FDSOI devices is analyzed using Multi-Subband Monte Carlo (MSMC) simulations, taking into account the main scattering mechanisms: phonons, surface roughness, and charged impurities in the access regions. In particular, the ballistic resistance (defined as the resistance of the channel in absence of scattering) was extracted from ballistic simulations,...
Influence of NiSi S/D incorporation on parasitic resistance (Rpara) fluctuation of FinFETs was investigated in detail. While the NiSi S/D enhances the on current of the FinFET thanks to the Rpara reduction, it also causes additional Rpara fluctuation. Through analysis of correlation of Rpara with fin thickness and gate-to-NiSi offset fluctuation, it is revealed that NiSi/n+-Si contact resistance component...
On-resistance is a term that occurs during high frequency switching. In this paper, the analysis of the on-resistance of FinFETs including quantum mechanical effect (QME), contact resistance, accumulation layer resistance, drift resistance and channel resistance is presented. Specific on resistance of FinFET is considered to be the series equivalent of contact resistance, drift resistance, accumulation...
The impact of gate-pitch scaling on device internal and external resistance is examined by advanced process and device modeling including distributed contact resistance model, mechanical stress and Monte Carlo (MC)-based stress-dependent mobility model. The contact resistance components and their major parameters in sub-50nm contact regime are analyzed by TCAD and transmission line modeling (TLM)...
To achieve high MOSFET drive current and speed in future technology nodes, potential bottlenecks such as high contact resistance should be resolved. In this paper, we review the technology solutions available for reducing the contact resistance between a metal silicide contact and the source/drain region. Novel approaches for reducing the electron and hole barrier heights between the metal silicide...
In this paper, we examined the applicability of the trench filled contact technique for the self-aligned dual metal contact for 3D MOSFET through both experiments and simulation. The proposed contact technique has the lower parasitic resistance and capacitance compared with the conventional silicide and with the elevated source/drain structure. Using this technique, the ITRS requirement for the source/drain...
This work reports on gate voltage dependent source and drain series resistance and associated barrier height in modified double gate Schottky MOSFETs with dopant segregation. We show that in our devices the series resistances is significantly reduced by lowering the Schottky barrier height (SBH). The series resistance and the barrier have been extracted using an external series resistance method and...
This paper demonstrates the integration of Al segregated NiSi/p+-Si S/D contact junction in p-FinFETs for parasitic series resistance reduction. Al is introduced by ion implant into p+ S/D region followed by nickel deposition and silicidation. Drive current enhancement of ~15 % is achieved without any degradation of short channel effects. This is attributed to the lowering of PhiBp of NiSi on p-Si...
Accurate measurement of contact resistance is crucial for advanced nanometer CMOS processes. An equally important requirement is to measure contact resistances in the same micro-environment as the device-under-test (DUT) will be used in real designs. With complicated interactions among various layout shapes in nanometer CMOS processes, test structures with adequate scalability is needed. In this paper...
We report the results of a systematic study to understand low drive current of Ge-based nMOSFET. The poor electron transport property is primarily attributed to the intrinsically low density of state and high conductivity effective masses. Results are supported by interface trap density (Dit) and specific contact resistivity (rhoc), which are comparable (or symmetric) for both n- and p-MOSFETs. Effective...
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