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The paper reports upon the design and characterization of a resistive O2 sensor, which is fully CMOS-compatible and is based on an ultra-low-power Silicon on Insulator (SOI) micro-hotplate membrane. The microsensor employs SrTi0.4Fe0.6O2.8 (STFO60) as sensing layer. Thermo-Gravimetric Analysis (TGA) Energy-Dispersive X-ray Spectroscopy (EDX), X-ray Diffraction (XRD) and Scanning Electron Microscope...
This paper presents a continuation of an investigation into the behavior of lead magnesium niobate-lead titanate, Pb(Mg0.33Nb0.67)0.65Ti0.35O3) (PMNT) thin film at high frequency through electromagnetic (EM) simulation. The purpose of this paper is to improve the electrical characteristics. The electrical characteristics were analyzed on CPW built on PMNT thin films. In this study, we focus on the...
The radiation resistance of silicon-on-insulator structures has been studied at low temperatures. High-energy electron irradiation (10 MeV, 1017 cm−2) caused a substantial change of resistance of polycrystalline silicon in SOI. Physical reasons for the observed changes have been discussed. The radiation-induced impurity segregation is likely responsible for the appearance of percolation type charge...
Backside roughness variation on incoming Silicon-On-Insulator (SOI) wafers can cause systematic variations in the dimensions of Al interconnects. Wafers with more backside roughness are more effectively cooled during reactive ion etching (RIE), resulting in a lower wafer temperature during the etch, and a larger line width. The backside roughness of the SOI substrate must be considered in order to...
A microswitch based on self-assembled carbon nanotube (CNT) arrays as micromechanical contact material has been demonstrated. The aligned CNT arrays are synthesized on microelectrodes and movable shuttle fabricated on a silicon-on-insulator (SOI) wafer. The CNT arrays are self-assembled on microstructures making mechanical contact between source and shuttle, and this contact is preloaded by the growth...
P-MOSFETs with HfO2 gate dielectric and TiN metal gate were fabricated on compressively strained SiGe layers with a Ge content of 50 at.% and electrically characterized. The devices showed good output and transfer characteristics. The hole mobility, extracted by a split C-V technique, presents a value of ~200 cm2/V·s in the strong inversion regime.
The dependence of the avalanche breakdown voltage on vertically linear doping gradient of the drift region based on Silicon-On-Insulator (SOI) lateral diffuse metal oxide semiconductor (LDMOS) is studied. Vertically linear doping profile (VD) of the LDMOS structure is exhibited to obviously improve safe of operation area (SOA) from the conventional uniform and variable linear doping structure. From...
We present an approach to scale Rext while maintaining control of short channel effects in scaled finFETs. For FETs with fins <;20nm, an enhancement of 19% in drain current was achieved in nFETs by incorporating Al at silicide-Si interface. This Al implantation while reducing the schottky barrier height for n-Si contact by 0.4 eV, does not degrade the integrity of the junction extensions or gate...
The difference in the number of contacts across different transistors and standard cells results in current variations across the channel. In this work, we present test structures to target this effect and characterize and quantify the impact on 45 nm SOI silicon. After comparing the impact of contact resistance between 65 nm and 45 nm silicon, we provide and analyze our 45 nm test structure results...
A new high voltage buried P+ layer membrane SOI (BP+M SOI) is proposed. Its Breakdown voltage (BV) is only decided by lateral breakdown voltage like Camsemi SOI. Introducing of P+ layer can effectively reduce specific on-resistance and alleviate self-heating effect (SHE). The electric characterizations are researched for the new structure by using 2D MEDICI software. The simulation results show that...
Fully integrated MESFETs have been shown to work on multiple commercial silicon-on-insulator (SOI) and silicon-on-sapphire (SOS) CMOS processes without changing a step in the process flow. The unique features of the MESFET including depletion mode operation, breakdown voltages in excess of 50 V, and easy to adjust, but well controlled threshold voltages have given the designers a cost-free way to...
Different thermal processes and substrates were used to investigate the time evolution of phosphorus loss due to segregation at the Si-SiO2 interface. Dose recovery occurred as phosphorus diffused into bulk silicon during furnace annealing. Dose loss increased when samples were cycled between silicon implantation and rapid thermal annealing (RTA). This implies that transient enhanced diffusion promotes...
A novel variation of lateral thickness (VLT) technique is proposed to bring a uniform surface electric field of SOI lateral high voltage devices. Comparing to the conventional RESURF device, the linear thickness of drift region increases the breakdown voltage by 40% while decreasing the drift resistance by 50%. Furthermore, single- or two-step drift thickness can be adopted to reduce fabrication difficulties...
We have developed a monolithic isolator that provides an isolation voltage of 4 kV and a signal transmission rate of 100 Mbps. Two circuit areas are isolated using 34 trenches on a bonded SOI with 3-mum-thick buried oxide. The inequality in the voltages applied to the trenches is reduced using polysilicon resistors parallel to the trenches, which increases the isolation voltage from 2.4 to 4.0 kV...
We report in this paper the fabrirication and the characterirization of FDSOI pMOSFETs with metallic source and drain exhibiting the best performance obtained so far on metallic source/drain devices, with Ion=345 nA/mum and Ioff=30 nA/mum at -1 V for a 50 nm gate length device. These results have been achieved thanks to a careful optimization of the source/drain to channel contacts, which can allow...
In this work, we demonstrate a novel SU8/SiO2 /PMMA trilayer nanoimprint technique to fabricate the silicon nanowire (SiNW) sensor used for gas detection. The SiNW sensor fabricated in our experiment is based on the silicon on insulator (SOI) substrate which is doped by boron with a dopant concentration of 8 times 1017 cm-3. Two nanowire sensors with different linewidths as well as a thin-film plane...
Both n- and p-type nano-thick piezoresistors are fabricated on SOI (silicon on insulator) wafers using micro-fabrication processes. Giant piezoresistance is measured and theoretically explained for nano-thick silicon resistors. Compared to bulk silicon, one order of magnitude higher piezoresistive coefficients are, for the first time, tested with 13 nm-thick n-type and 9 nm p-type samples. Surpassing...
We report on the experimental characterization of a single crystal silicon square-plate microresonator. The resonator is excited in the square wine glass (SWG) mode at a mechanical resonance frequency of 2.065 MHz. The resonator displays quality factor of 9660 in air and an ultra-high quality factor of Q = 4.05 times 106 in 12 mtorr vacuum. The SWG mode may be described as a square plate that contracts...
This paper reviews special RF/microwave silicon device implementations in the back-wafer contacted Silicon-On-Glass (SOG) Substrate-Transfer Technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the resistive/capacitive parasitics of the silicon devices can be minimized by a direct two-sided contacting. Focus is placed...
We have successfully fabricated uniaxially strained SOI FinFETs with high electron mobility and low parasitic resistance. The electron mobility on (110) sidewall surfaces was found to surpass the (100) universal mobility by the subband engineering through uniaxial tensile strain along <110>. Thanks to this high electron mobility enhancement and the relatively low parasitic resistance, high I...
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