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In this work, we deal with securing the real-time systems by providing them with additional hardware watchdog timers. This paper proposes the basic concept of the multiple hardware watchdog timers system and describes the proposed architecture of the system providing 256 hardware watchdog timers. It deals with the particular implementation of the system in the FPGA programmable device. The results...
We present a runtime system that uses the explicit on-chip communication mechanisms of the SARC multi-core architecture, to implement efficiently the OpenMP programming model and enable the exploitation of fine-grain parallelism in OpenMP programs. We explore the design space of implementation of OpenMP directives and runtime intrinsics, using a family of hardware primitives; remote stores, remote...
Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. A multicore FPGA platform with cache-integrated network interfaces (NIs) is presented, appropriate for scalable multicores, that combine the best of two worlds -the flexibility of caches (using...
Speeding up the data rate in today's fiber optical networks requires a sophisticated higher order modulation. For this purpose high speed ADCs and DACs are necessary with sampling rates above 25 GS/s and a resolution of 6 bit. This drives the combined data rate to 150 Gbit/s. To realize a cost-efficient and fully scalable measurement system for the characterization of the high speed ADCs and DACs,...
A firewall's complexity and processing time is known to increase with the size of its rule set. Empirical studies show that as the rule set grows larger, power consumption and delay time for processing IP Packets particularly on Hardware firewalls increases extremely, and, therefore the performance of the firewall decreases proportionally. This paper present a new FPGA (field programmable gate arrays)...
Nondeterminism of multi-clock systems often complicates various system validation processes such as post silicon debugging and at-speed testing, which has brought many difficulties to system designers and testers. The major source of nondeterministic behaviors is clock domain crossing, because the clocks that determine the timing of events are sensitive to variations. In this paper, we propose a general...
Field-Programmable Gate Arrays (FPGAs) are becoming increasingly important in embedded and high-performance computing systems. They allow performance levels close to the ones obtained from Application-Specific Integrated Circuits (ASICs), while still keeping design and implementation flexibility. However, to efficiently program FPGAs, one needs the expertise of hardware developers and to master hardware...
This paper describes an alternative approach to direct mapping loops described in high-level languages onto FPGAs. Different from other approaches, this technique does not inherit from software pipelining techniques. The control is distributed over operations, thus a finite state machine is not necessary to control the order of operations, allowing efficient hardware implementations. The specification...
It is time consuming to design a complex system which has multi-function and mutual exclusion. In this paper, the design which flows of complex control system with Mutual Exclusion is divided into abstraction route and embodiment route. In the abstraction route, functions of the system are transferred to processes by using obtained or innovated algorithms and the processes are divided into modules...
This paper presents a novel method to perform on-the-fly attestation of hardware structures loaded to reconfigurable devices. Given that a loadable hardware structure to a reconfigurable device is described by a binary bitstream, the hash value of this bitstream can be calculated to validate the hardware structure. To optimize this attestation, the hash value computation is implemented in hardware...
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