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Multimedia MPSoC (Multi-Processor System-on-Chip) has been widely used in today's consumer electronics. As many memory intensive IP (Intellectual Property) cores are integrated into a single chip, the performance of shared memory has been a critical issue. Conventional memory scheduling policies just schedule the existing requests in the queue and waste the potential scheduling space because they...
To efficiently and effectively debug silicon bugs, a promising solution is to determinize the chip, so that the buggy silicon behaviors can be faithfully reproduced on a RTL simulator. In this paper, we propose a novel scheme, named LDet, to determinize a chip through removing the nondeterminism in transfers crossing different clock domains, even when these clock domains are heterochronous. The key...
Nowadays high-performance multimedia SoC design always integrates a variety of function units (FU) into a single chip and these FUs impose great stress on the shared memory system. To improve the memory system utilization and meet a wide range of bandwidth and latency requirements of these FUs, a well-designed memory scheduler that takes the quality-of-service (QoS) into account must be adopted. In...
For many Operating Systems and device drivers, memory copy is the most time-consuming operation which has always been paid special attention. In this paper, we propose a processor DMA based memory copy hardware accelerator with the goal to reduce the instructions executed on CPU, and exploit the parallelism between computing and data transfer in memory copy. This is accomplished by taking advantage...
Nondeterminism of multi-clock systems often complicates various system validation processes such as post silicon debugging and at-speed testing, which has brought many difficulties to system designers and testers. The major source of nondeterministic behaviors is clock domain crossing, because the clocks that determine the timing of events are sensitive to variations. In this paper, we propose a general...
Binary translation is one of the most important approaches for system migration. However, software binary translation systems often suffer from the inefficiency and traditional hardware-software co-designed virtual machines require the unavoidable re-design of the processor architecture. This paper presents a novel hardware-software co-designed method to accelerate the binary translation on an existing...
For most SoCs, off-chip DRAM is an important resource that is shared by many heterogeneous function units(FU).To meet different memory access requirements by these FUs,it is crucial that the memory subsystem is capable of providing different quality of service(QoS).Due to the nature of DRAM, the available bandwidth greatly depends on the memory access sequence. However,conventional schedulers are...
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