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Ge is an indirect band gap material. The band structure of Ge is a strong function of strain and alloy composition, and a transition from an indirect to a direct band gap has been observed for y∼6–10% for relaxed Ge1_ySny indicating the possibility of widespread applications of Ge-based photonic devices. The pseudomorphic nature of the Ge-based alloy layer on a substrate is important to keep dislocation...
This work investigates light emission from silicon with embedded Sn nanocrystals. The composition of the nanocrystals is determined to be pure Sn by atom probe tomography, and the light emission is strongest when the nanocrystal structure is closest to the host Si lattice diamond structure.
We have developed the epitaxial growth technology of Ge1−xSnx and related group-IV materials. The crystalline properties and energy band structure have been investigated for integrating group-IV semiconductors into Si ULSI platform.
We report solar-bind UV detectors based on nanophotonic metal-oxide-semiconductor (MOS) structures. The nanostructured metal acts as the UV absorber, while the large meta/oxide interfacial energy barrier (>4 eV) eliminates the solar response. Quantum efficiencies >100% are demonstrated due to hot-electron induced avalanche gain in Si.
The understanding of the switching mechanisms in resistive random access memory is of interest as one can use the fundamental mechanisms to better design the memory structure for enhancing both switching and reliability performance. Various analytical methods have been explored to better understand the wear-out and eventual failure mechanisms of RRAM stacks. This includes atomic-scale characterization...
A laterally diffused metal oxide semiconductor (LDMOS) has been fabricated on a 12.2 μm buried oxide (BOX) silicon-on-insulator (SOI) substrate, successfully achieving a breakdown voltage of over 2000 V. This paper describes the proposed drift structure for SOI LDMOS. The proposed LDMOS drift structure adopts SOI reduced surface electric field (SOI RESURF) technology, which uses the BOX layer to establish...
We investigate energy band structures of Si1−xSnx compound alloy in zincblende structure using interacting qasi-band (IQB) model. The previous IQB model has been developed for three element compound semiconductors such as A1−xBxD. To apply IQB for Si1−xSnx, we here extend the IQB for four element compounds and calculate the electronic structures of virtual alloy as Si1−xSnxSi1−ySny, where x=y. Diagonalizing...
Wafer level integration of photonic detectors on a silicon substrate is expected to dramatically bring down the cost of detectors. State-of-the-art manufacturing of focal plane arrays (FPA) is based on wafer level processing including mesa delineation, surface passivation, metal evaporation, and indium deposition, followed by a die-level fabrication with dicing, flip-chip bonding to a silicon read-out...
Sharp electrically conductive structures integrated into micro-transfer-print compatible components provide an approach to forming electrically interconnected systems during the assembly procedure. Silicon micromachining techniques are used to fabricate print-compatible components with integrated, electrically conductive, pressure-concentrating structures. The geometry of the structures allow them...
Low cost through silicon via (TSV) technology is a key enabler for the future performance growth of various semiconductor devices. Deep etching and solder filling for TSV through pre-stacked silicon wafers make the TSV process much simpler. Polymer insulator also contributes to stress reduction and conformal insulation. In this paper, we investigate the barrier effect of polymer insulators on metal...
In this paper, a new on-interposer passive equalizer was proposed for the next generation High Bandwidth Memory (HBM) with 1024 I/O lines and 30 Gbps data rate. It is a coil-shaped shunt metal line and embedded on a ground plane to reduce area consumption on a signal layer and to maintain fine pitch of 10 um. The proposed equalizer utilizes its inductance and resistance to perform a high-pass filter...
MEMS devices are continuous evolving to achieve smaller size and lower cost with improved performance. The Through silicon via (TSV) technology offers a promising approach from the perspective of MEMS device packaging and integration. In this paper, we report our latest progress on wafer level packaging of MEMS devices by via-last process. The 200mm MEMS wafer was bonded with a glass cap wafer. Then,...
The original purpose of the Re-Distribution Layers(RDL) was to assist in the adaption of metal bumping and flipchip packaging technologies, by the addition of the metal anddielectric layers onto the wafer surface to re-route the legacydesigned irregular peripheral I/O layout, into a new area arraybond pads layout to facilitate a balanced metal bumps and flipchip bonding. The redistribution layer technology...
We improved a through-silicon via (TSV) revealprocess comprising direct Si/Cu grinding (simultaneousgrinding of Si and Cu) and residual metal removal. In thisimproved process, direct Si/Cu grinding was performed byusing a novel grinding wheel (vitrified-bond type) and cleaningthe wheel with a high-pressure micro jet. Instead of electrolessNi-B plating, electroless Sn plating was then performed tocover...
The continual downscaling of CMOS transistors, as predicted by Moore's Law, has faced tremendous challenges in terms of performance and cost reduction. Through Silicon Via (TSV) technology provides an alternative "More than Moore" solution for system level integration, resulting in smaller form factor, reduced power consumption and large bandwidth for higher data transfer rate. Via-last...
Contact resistance at the transistor source/drain becomes a bottleneck for modern Si CMOS technology. To seek for contact solutions, this paper compares metal-insulator-semiconductor (MIS) contacts and metal-semiconductor (MS) direct contacts in terms of contact resistivity and CMOS compatibility. On p-type substrates, due to the favorable surface Fermi level pinning, MS contact has absolute advantage...
In this paper, some key fundamental aspects of Metal / Insulator / Semiconductor contacts as well as practical issues occurring with their implementation are reviewed in order to fully comprehend the opportunities and limitations of this approach.
A conventional back end of line (BEOL) post-lithography rework process is usually considered as a non-critical process compared to other process steps in a silicon flow in advanced technologies. This paper discusses the impact of this non-critical process to defectivity and yield. For advanced technology nodes using a tri-layer trench first lithography stack, the conventional rework process was proven...
For the last decade, paraelectric BaxSr1−xTiO3 (BST) thin films have been especially studied to fabricate MIM capacitor for capacitance tuning applications. This paper describes the mechanisms of cracks apparition under BST stacked MIMIM capacitors (Metal Insulator Metal Insulator Metal) built on silicon substrate. The methodology used in this study to have a further understanding of this phenomenon...
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