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In this paper, we have proposed a new device structure of schottky-collector bipolar charge plasma transistor (SC-BCPT) with an extended base of thickness (tB = 25 nm). The charge plasma concept eliminates different doping requirements for emitter and base regions, as a result, simplified fabrication process and improved current gain (ß). However, extended base concept yields improved cut-off frequency...
Down-scaling has been the leading paradigm of the semiconductor industry since the invention of the first transistor in 1947. This paper discusses the development of a unique technology for creating atomic-scale devices in silicon. We will introduce single atom transistors and how we are systematically demonstrating the components of a quantum integrated circuit at the atomic-scale towards the development...
Power Management Integrated Circuits (PMIC) chips contain large power switches - usually LDMOS transistors, along with low current control circuitry. During transistor switching, charge carriers are injected into the substrate and affect the surrounding devices. In junction isolated technologies, hole injection is effectively suppressed using highly doped n-type layers, while electron injection requires...
Some driving technologies of the digital system design have faced a number of physical limits in the last 20 years. A promising technique to mitigate the effects of the limits is Approximate Computing or Adequate Precision Computing. The memory hierarchy and processor architecture have played key roles in the microprocessor system development. However, the major focus in approximate computing has...
Scaling down of the semiconductor devices from micro to Nano scale has now become the trend for the electronics industry and it is the only hope that can ensure lesser power consumption and also reliability. Ultra thin MOSFET's, Double Gate MOSFET's, FINFET and now the latest development is the Nanowire FET. The nanowire FET is a revolutionary device as the gate is all around the channel which provides...
This paper represents diameter and logic voltage level optimizations of 6-Silicon Nanowire Transistors (SiNWT) SRAM. This study is to demonstrate diameter of nanowires effects at a different logic voltage level (Vdd) on the static characteristics of Nano-scale SiNWT Based SRAM Cell. Noise margins (NM) and inflection voltage (Vinf) of transfer characteristics are used as limiting factors in this optimization...
The light-emitting transistor (LET) is examined as a fundamental circuit element for electronic-photonic integration. Basic device properties, methods of integration, and simple electronic-photonic circuits built upon the LET are examined. Novel materials, methods, and devices for heterogeneous integration are also presented.
Residual levels of stress remaining after device fabrication have been characterized in the base and emitter regions of shallow-trench-isolated complementary npn and pnp transistors on (100) silicon utilizing uniaxial stress measurements. A residual biaxial stress of approximately 160 MPa has been found in the active regions of the npn transistors, whereas negligible residual stress is observed in...
This paper reviews our recent work on Si and SiGe THz sources that generate high-power coherent radiation. Our design approach blends the optimization of device operation near or above fmax with unconventional circuit topologies and energy-efficient electromagnetic structures. Using a 130-nm SiGe HBT process (fmax=3D280 GHz), our 320-GHz transmitter produces a record radiated power (3.3 mW) and DC-to-THz...
In this paper, effects of expected physical limits of CMOS technology on the performance of small-scale System-on-Chips (SoCs) are described. The exponential progress of CMOS technology has entered to the saturation phase. This could be called, if we like, a third phase of the Moore's law. In this third phase of development, the peak-performance of SoCs is not any more in the main concern. Instead...
In this paper, we propose an advanced tunneling field-effect transistor (TFET) structure. The fabrication method of proposed TFET is designed. The characteristics of the proposed TFET are investigated by device simulation.
We fabricate and characterize p-channel double quantum dots (DQDs). The DQDs are formed on a silicon-on-insulator (SOI) wafer and integrated with a single hole transistor (SHT) as a charge sensor. We observe charge stability diagram of the DQDs in the characteristic of the charge sensor. Furthermore, few-hole regime in the DQDs is clearly obtained.
Reconfigurable Silicon nanowire Schottky Barrier transistors (RFETs) with configurability to be programmed as n/p-type polarity are promising for future integrated circuits. In this work, the tunable polarity characteristics of RFETs are investigated. TCAD simulations have been performed for RFETs-based INV, NOR, NAND logic gates and SRAM cell. 4-terminal RFETs presented show the potential of programmable...
This work reveals the impact of quantum mechanical effects on the device performancce of n-type silicon nanowire transistors (NWT). Here we present results for two Si NWTs with circular and elliptical cross-section. Additionally we designed both devices to have identical cross-section in order to provide fair comparison. Also we extended our discussions by reporting devices with five different gate...
In this paper, we propose a novel sandwiched-gate inverter by using of an NMOS GAA together with a donut-type PMOS. The DC operation and the transient performance of the proposed inverter were investigated with 3D TCAD simulations. The proposed inverter exhibits a correct inverter operation with a high noise margin and speed.
Wide band-gap materials such as Gallium Nitride (GaN) and Silicon Carbide (SiC) offer improved performance for power electronic devices compared to traditional Silicon (Si) power semiconductor devices. This paper investigates a 600V GaN & Silicon CoolMOS transistor application in 400W single phase continuous conduction mode (CCM) Boost PFC converter circuits with GaN, SiC and ultrafast silicon...
Conventional planar transistors have been used throughout the semiconductor industry for the past several decades. Further miniaturization of conventional devices has been proven to be a significant challenge and thus the industry has transitioned to Planar Fully Depleted FETs and FinFETs. As we look out at technologies beyond 7nm node there are many barriers which appear to limit the scalability...
Two-dimensional (2D) atomic sheets yield collective properties of mechanical flexibility, electrical control, optical transparency and high surface-to-volume ratio, which hold promise for advanced flexible nanoelectronics and sensors. This work explores two newly emerging 2D materials, silicene and phosphorene (the Si and P equivalent to graphene) and their air-stability and device study. The debut...
To investigate self-heating effects in double gate MOSFETs, a simulator solving self-consistently the Boltzmann transport equations (BTE) for both electrons and phonons has been developed. A Monte Carlo (MC) solver for electrons is coupled with a direct solver for the phonon transport. This method is particularly efficient to evaluate accurately the phonon emission and absorption spectra in both real...
An open boundary-conditions full-band quantum transport formalism with a plane-wave basis based on empirical pseudopotentials is used to self-consistently simulate transistors in the sub-1 nm technology node, with one-dimensional silicon nanowires, armchair-edge graphene nanoribbons, and zigzag-edge carbon nanotubes as the channel. The electrostatic potential energy and charge density distribution...
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