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Recently, Assertion-Based Verification (ABV) has been significantly improved and used not only in academia but also in industry. In this paper, we present a new assertion checking approach that dynamically interprets a software-defined assertion checker during run-time. In contrast to the state-of-the-art hardware checker, the presented method compiles its checker to instructions, which can be changed...
Efficient estimation of power consumption is vital when designing large digital systems. The technique called power emulation can speed up estimation by implementing power models alongside a design on an FPGA. Current state-of-the-art power emulation methods construct models using various custom techniques, but there is no study on how the existing methods relate to each other nor how their differences...
Since its introduction, SystemC-AMS extensions to SystemC have been used in several applications to model the analog part of a heterogeneous SoC. In this case, the SoC is usually a pure simulation model where the digital part is modeled using SystemC. If an emulation verification environment is used, the digital part of the SoC would be running on the emulator while the analog part, modeled with SystemC-AMS,...
Systems on chip (SoC) nowadays, have become heterogeneous in nature. They can be composed of a mix of analog and digital components. In some verification environments, SystemC models the digital components and SystemC-AMS extensions can be used to model the analog part. In an emulation environment, the digital components would be probably running on the emulator while the SystemC-AMS components would...
SRAM-based FPGAs are very sensitive to harsh conditions, like radiations or ionizations, and need to be hardened to insure correct running. To validate any fault tolerant solution for these SRAM-FPGA, fault injection campaigns must be conducted carefully. In this work, we present a new design flow to perform localized internal fault injection on specific parts of a Design Under Test (DUT). To achieve...
In the paper, two methods of ensuring high quality of the memory built-in self-test tools are presented. The described ideas illustrate general methods and are applicable to any commercial memory BIST tool. The first solution describes controller emulation in order to validate each step of the real controller's operations. The second approach presents a way to determine the test algorithms' fault...
In this paper, an online RTL-level scan chain methodology is proposed to reduce debugging time, effort and accelerate IP emulation. Run-time changes of the values of the signals of the IP during execution-time can be done by the proposed scan-chain methodology. A utility tool was developed to help ease this process. Our experiment shows that, the area overhead is neglected compared to the gained performance...
To improve debugging turnaround time of complex System-on-chip (SoC) designs on FPGA based logic emulation systems, it is important to minimize the iterations through design recompilation or FPGA reconfiguration process for validating repeated debugging changes. This paper presents a methodology for modeling debugging changes in terms of standalone assertion statements and evaluating their effect...
In this paper, we present an Assertion based functional verification methodology for DDR type memory cores. The methodology is based on formulating DDR pattern properties extracted from JDEC standard which are then translated to synthesizable DDR Type SVA Protocol checkers for HW Emulation Platforms. The protocol checker verifies the validity of command sequences, command Timing, Mode Registers settings,...
Field Programmable Gate Array (FPGA) based logic emulators, used for functional verification of large and complex System-on-chip (SoC) designs are characterized by two conflicting requirements - execution speed and signal visibility. Achieving 100% signal visibility in post-processing debug for long emulation runs impacts execution speed and requires large amount of disk space. Techniques like combinational...
Hybrid functional verification and debug systems which combine high execution speed of logic emulators and full observability and controllability of software simulators are widely used, but suffer from scalability problem since software simulators cannot handle large and complex System-on-chip (SoC) designs efficiently, restricting their application to only relatively small designs. This paper presents...
For functional verification, logic emulators offer speed of execution while software simulators provide full observability and advanced debugging techniques. Hybrid functional verification systems, which run long test sequences in an emulator and upon error detection, transparently switch-over to simulation based debugging are extensively used. These systems suffer from scalability problem since simulators...
Practical experience of pre-silicon verification of the processor core is presented. The proposed methodology gives good results, good coverage, and requires a short verification time period.
In medical research it is of great importance to be able to quickly obtain answers to inquiries about system response to different stimuli. Modeling the dynamics of biological regulatory networks is a promising approach to achieve this goal, but existing modeling approaches suffer from complexity issues and become inefficient with large networks. In order to improve the efficiency, we propose the...
This paper describes a collaborative effort between Mentor Graphics and Portland State University to introduce hardware emulation into the undergraduate and graduate electrical and computer engineering curriculum. We detail several parallel approaches that address a need for both broad exposure to the concepts of hardware emulation and more in-depth experience with transaction-based verification.
Hybrid embedded testbench acceleration (HETA), a new approach to reduce communication overhead in hardware accelerators, speeds up simulation of chip prototypes by avoiding the communication between hardware and software. Experimental results on an industry design show that the proposed HETA approach is about 10 times faster than a commercial hardware accelerator and with only 0.57% hardware overhead.
With the advent of increasingly complex systems, the use of traditional power estimation approaches is rendered infeasible due to extensive simulation times. Hardware accelerated power emulation techniques, performing power estimation as a by-product of functional emulation, are a promising solution to this problem. However, only little attention has been awarded so far to the problem of devising...
In HW/SW co-simulation based logic verification systems, the design under test (DUT) is executed on an FPGA based emulator and the behavioral testbench written in some high level language like C or HDL is run on a SW simulator or a general purpose CPU. In such systems it is essential to reduce the communication between SW and HW sides to enhance overall verification speed. Therefore it is of significant...
FPGAs are subjected to SEU faults. Fault emulation methods are used to verify the behavior of the system in the presence of fault. In this paper an automated fault emulation approach is presented. An original, fully automated extraction of SEU fault sources is introduced and the injection procedure for various types of faults in FPGA configuration and user memory is explained. Faults are injected...
Targetless logic emulation refers to a verification system in which there are no external hardware targets interfacing with the emulator. In such systems input stimuli to the DUT come either from a user provided vector file or a HDL testbench running on a software simulator and the DUT runs on hardware based logic emulator. Many users use such targetless environment for automated long running verification...
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