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Reliability is a major concern for embedded systems. Semiconductor devices used to implement them can suffer from various environmental perturbations. This is more evident when considering SRAM-based FPGA. Perturbations are very frequent and they can limit FPGA's usability. In this paper, a new fault tolerance approach is presented which try to take advantage of partial dynamic reconfiguration provided...
SRAM-based FPGAs are very sensitive to harsh conditions, like radiations or ionizations, and need to be hardened to insure correct running. To validate any fault tolerant solution for these SRAM-FPGA, fault injection campaigns must be conducted carefully. In this work, we present a new design flow to perform localized internal fault injection on specific parts of a Design Under Test (DUT). To achieve...
Existing SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Effects (SEE) phenomena in harsh environments. To protect applications running on SRAM-based FPGAs from SEE, those applications mainly relay on resources redundancy approaches, which involve significant resources overhead. New proposed fault mitigation approaches use Partial Dynamic Reconfiguration to overcome...
Reconfigurable system on Chip (RSoC) is seen as a possible future trend in embedded electronic. This work focuses on the management of dynamically reconfigurable resources (eg. FPGA) using a real time operating system (RTOS) especially designed for such platform. Scheduler and placer are crucial OS services to allow for online management of the computing resources. In this work we introduce multi-shape...
Single Event Upset (SEU) is a major concern for SRAM-based FPGAs where a simple bit-flip can lead to an abnormal execution. We present in this paper, a new fault tolerance method based on hardware BER (Backward Error Recovery) to protect/correct system against the occurrence of transient faults. We use the partial dynamic reconfiguration offered by Xilinx Virtex-5 FPGAs to ensure hardware checkpoint...
This paper aims to provide Hardware/Software (Hw/Sw) codesign guidelines for system-on-chip field-programmable gate array-based sensorless ac drive applications. Among these guidelines, an efficient Hw/Sw partitioning procedure is presented. This Hw/Sw partitioning is performed taking into account both the control requirements (bandwidth and stability margin) and the architectural constraints (e.g...
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