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SRAM-based FPGA devices are becoming a suitable platform for implementing modern Systems On Programmable Chip (SOPC) due to their high reconfigurability, low cost and availability. The high performance SOPCs are often powered by multiple embedded microprocessors. FPGA devices are susceptible to radiation which causes soft-errors in their configuration memory. This paper proposes a soft error recovery...
Mission critical and reliable systems on FPGA require error mitigation and recovery techniques to protect them from the errors caused by high energy radiation also known as Single Event Upsets (SEU). Different solutions have been reported with different trade-off of area-overhead and fault latency. We propose a low area-overhead self-reparable procedure based on an internal error recovery mechanism,...
This paper presents a compact, low-cost, on-line error-detection architecture for a 32-bit hardware implementation of the AES. The implemented AES is specially designed for FPGA-based embedded applications, since it is tuned to specific FPGA logic resources. The on-line error-detection is based on parity codes. The parity prediction is implemented in the AES encryption, decryption, and key expansion...
We propose a low hardware overhead mechanism for internal FPGA configuration check and repair. The approach is effective against soft errors in the configuration memory (i.e., the errors caused by high energy radiation also known as Single Event Upsets). The proposed recovery mechanism occupies less hardware resources and has the shortest fault recovery time than the solutions reported so far.
FPGAs are subjected to SEU faults. Fault emulation methods are used to verify the behavior of the system in the presence of fault. In this paper an automated fault emulation approach is presented. An original, fully automated extraction of SEU fault sources is introduced and the injection procedure for various types of faults in FPGA configuration and user memory is explained. Faults are injected...
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