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A lot of research has been done on efficient implementation of RS code encoders and decoders as VLSI chips. However, none of them tries to seek a unified approach for solution to obtain VLSI hardware for RS encoders and decoders which can be easily configured for use across a large set of application areas with varying specifications. In this paper, a novel parallel RS decoding algorithm suitable...
Requirements and design phases of hardware and software intellectual processing of intensive data streams in real time have been examined. Design principles of hardware and software tools have been proposed. Translation of processing algorithms into hardware and software tools has been described. The basic structure of parallel-flow system with data exchange through multiport memory has been proposed.
Image scaling is one of the widely used techniques in various portable devices to fit the image in their respective displays. Traditional image scaling architectures consume more power and hardware, making them inefficient for use in portable devices. In this paper, a low complexity image scaling algorithm is proposed. In the proposed algorithm, the target pixel is computed either by bilinear interpolation...
This paper presents a novel VLSI hardware architecture for the real-time high-throughput implementation of the HEVC deblocking filtering. Based on the proposed implementation-friendly boundary judgment method, a dedicated multi-parallel architecture composed of four parallel filtering cores, parallel luma/chroma filtering and parallel vertical/horizontal edges filtering is presented. Experimental...
In the field of RFID technology, a power efficient tag anti-collision protocol plays an important role in the entire system based on this technology. The query Tree scheme is one of the most important anti-collision protocols for RFID technology. Researchers have developed different Query algorithm with improved features, each time reducing the number of query iteration and idle slots. The EPC Gen...
Firstly, an implementation-friendly interpolation filter algorithm is proposed in this paper. It can save 19.6% processing time on average with negligible coding quality degradation. Then based on the proposed algorithm, an optimized interpolation filter VLSI architecture, composed of the reused data path of interpolation, efficient memory organization and the pipeline interpolation filter engine...
This paper presents an efficient VLSI architecture for the implementation of Motion Estimation (ME) for real-time video processing using New Three Step Search Algorithm (NTSS). The proposed architecture employs sequential processing of pixels with a view to reduce the hardware complexity and achieve real-time speed requirement simultaneously. A novel memory addressing scheme has been proposed which...
This paper proposes to implement a hardware efficient light weight encryption algorithm based on Light Encryption Device (LED). The hardware efficiency of a Light Encryption Device (LED) is mainly determined by the implementation of the S-Boxes and the Mix Columns operation. In order to reduce the computations involved, these two round operations are combined into a single transformation step called...
This paper presents a new design and a fast technique for implementation of a 32-bit decimal floating-point (DFP) logarithmic computation to efficiently calculate radix-10 logarithm of a decimal number. Conventional techniques first convert decimal inputs to binary, then perform base-2 logarithm operations, and finally results are converted back to decimal radix. It sometimes causes errors due to...
High performance implementations of unary functions are important in many applications e.g. in the wireless communication area. This paper shows the development and VLSI implementation of unary functions like the logarithmic and exponential function, by using a novel approximation methodology based on parabolic synthesis, which is compared to the well known CORDIC algorithm. Both designs are synthesized...
Motion estimation plays an important role in inter-frame prediction for the video coding standards such as H.264/AVC, MPEG-2, MPEG-4, VC-1, and so on. Its huge computation complexity, however, makes it difficult to achieve real-time coding for the HDTV1080p. In this paper, we propose a dynamic search range algorithm which reduces about 80% of search points in full search algorithm for the H.264/AVC...
Bidirectional motion estimation is an efficient algorithm which can solve the problem of holed and overlapped regions for motion compensated frame interpolation in frame rate up-conversion applications. This paper proposed an efficient VLSI architecture for this algorithm using multi-resolution frames to reduce the hardware resource. The initial motion vectors (MVs) in bidirectional motion estimation...
In order to select a new Standard Hash Algorithm (SHA-3) which supplies more security, a public competition was organized by NIST in 2007. Up to now, 14 candidates have passed the 2nd round. In this paper, we focus on two of these candidate algorithms, namely BLAKE and Shabal. We present the common structure for all the SHA3 candidates. We also design the VLSI circuit and give the hardware evaluations...
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent register transfer level (RTL) description of hardware. This flow uses an intermediate representation which is an orthogonal factorization of the program behavior into control, data and memory aspects, and is suitable for the description of large systems. We show that optimizations such as arbiter-less...
For VLSI design which have large collection of objects to be constrained, clear sequence of execution of constraints is important using constraint-satisfaction method for proper execution to avoid constraint loop at algorithmic level. The objective of this paper is relaxation based constraint sequence solving technique applied to the backtrack step of backtrack search solver, with the goal of increasing...
Spread Spectrum applications require a set of sequences with individually peaky auto-correlation and pair-wise cross-correlation. Obtaining such sequences is a combinatorial problem. If the auto-correlation and cross-correlation are taken in the aperiodic sense then there are hardly any theoretical aids available. Thus the problem of signal design referred to above is a challenging problem for which...
Advent of Matrix Theory has greatly aided and simplified the analysis for variety of signal processing algorithms. It has been proven that matrix notation is convenient for representation of signals and to perform operations on them. Many problems such as signal modeling, Wiener filtering and spectrum estimation require finding the solution or solutions to a set of linear equations. Some of the common...
This paper presents the first ASIC implementation of an LR algorithm which achieves ML diversity. The VLSI implementation is based on a novel hardware-optimized LLL algorithm that has 70% lower complexity than the traditional complex LLL algorithm. This reduction is achieved by replacing all the computationally intensive CLLL operations (multiplication, division and square root) with low-complexity...
Variable block size motion estimation (VBSME) is becoming the new coding technique in H.264/AVC. This paper presents a low-power VLSI implementation for full-search VBSME. Compared to existing hardware architectures and implementations for VBSME, the proposed design employs a fast full-search block matching algorithm to reduce power consumption, while preserving the optimal solution and the throughput...
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