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The following topics are dealt with: VLSI design; embedded system design; cryptographic hardware engineering; reconfigurable systems; mixed signal design; high performance design; design for reliability; architecture level design; memory design; and nanocomputing.
In 2011-2012, the European ICT research priorities are focused on a set of Challenges with mid-to-long term goals that require trans-national collaboration. Each Challenge is addressed through a limited set of objectives that form the basis for Calls for Proposals and lead to EU-funded research projects. One of the Challenges addresses "Alternative Paths to Components and Systems", it covers...
Microfluidics-based biochips are revolutionizing high-throughput sequencing, parallel immunoassays, clinical diagnostics, and drug discovery. These devices enable the precise control of nanoliter volumes of biochemical samples and reagents. Compared to conventional laboratory procedures, which are cumbersome and expensive, miniaturized biochips offer the advantages of higher sensitivity, lower cost...
Consumer electronics (CEs) is mainly characterized by its heterogeneity in products and markets. Moreover, large companies like Google, YouTube, Myspace, are revolutionizing the way to provide information contents. Today, several new CE devices have been introduced in the marketplace for receiving, visualizing, communicating, creating, and sending information. This changing implies that end-users...
Reconfigurable technology offers great advantages in bioinformatics applications vs. general-purpose computing. The presentation outlined in this paper looks into the attributes of several bioinformatics algorithms which make them suitable for reconfigurable computing, the resulting architectures, and their performance tradeoffs vs. general-purpose computers, graphics processor units (GPU) and VLSI.
Advances in nanotechnology and the research of new materials has led to the elaboration of nano-components with novel properties and functions. Exploring how those novel components could be used to devise future computer architectures, complementing rather than supplementing CMOS technology, is a new research subject known as Nanocomputing. In this talk we will present the major challenges of such...
Stored Unibit Transfer (SUT) has been recently proposed as a redundant high-radix encoding for the channels of a Residue Number System (RNS) that can improve the efficiency of conventional redundant RNS. In this paper we propose modulo 2n±1 forward and reverse converters for the SUT-RNS encoding. The proposed converters are based on parallel-prefix binary or modulo adders and are therefore very efficient.
A novel clock tree synthesis (CTS) method is proposed that improves the reliability of an integrated circuit system through reducing the peak current on the power/ground rails drawn by the clock tree buffers. The proposed CTS method entails the integration of XOR gates at one level of the clock tree to enable polarity assignment for peak current reduction. Unlike previous polarity assignment methods,...
Nowadays, design issues related to physical design and scalability are becoming the main bottlenecks of modern tools for technology mapping, limiting the usage of large cells. On the other hand, the generation of regular macro cells, such as compound gates, are becoming interesting from the manufacturing point of view, but they need to be properly integrated into the existing industrial design flows...
Asynchronous system design in recent years has reemerged as an important vehicle in the field of high performance, low power and secure computing. On the other hand Binary Decision Diagrams (BDDs) have found significant applications for many years in the design, synthesis, verification, and testing of VLSI circuits. In this paper we have presented the design of a hybrid Domino PTL-CMOS based 2-bit...
Looping operations impose a significant bottleneck to achieving better computational efficiency for embedded applications. To confront this problem in embedded computation either in the form of programmable processors or FSMD (Finite-State Machine with Datapath) architectures, the use of customized loop controllers has been suggested. In this paper, a thorough examination of zero-cycle overhead loop...
In this work a comprehensive exploration of Binary Sequence Generators (BSG) is offered, focusing on an alternative type of BSG (radix-2 counter) presenting low design complexity and interesting speed characteristics, based on 2D Cellular Automata (CA). Various “seed” configurations are explored and two architectures are examined, defining the most appropriate CA in terms of speed, silicon area and...
Continuous scaling in CMOS fabrication process makes circuits more vulnerable to process variations, which results in variable delay, malfunctioning, and/or leaky circuits. Caches are one of the biggest victims of process variations due to their large sizes and minimal cell features. To mitigate the impacts of process variations on caches, we propose to localize the effects of process variations at...
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