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A Narrowband Differential Low Noise Amplifier (DLNA), applicable for Global Positioning System receivers, with center frequency of 4.1GHz and Bandwidth of 90MHz using 180nm rf CMOS process parameters is designed in this paper. Rigorous optimization is carried out for the following parameters-Input and Output Impedance Matching, Gain, Bandwidth, Noise Figure, Power Consumption, 1dB Compression Point,...
This paper proposes the regenerative amplifier based on the Colpitts oscillator topology. The positive feedback amount was optimized analytically in the circuit design. The proposed regenerative amplifier was fabricated in 65 nm CMOS technology. The measurement results showed 28.7 dB gain and 6.4 dB noise figure at 2.55 GHz while consuming 120 μW under the 0.5-V power supply.
The millimeter-wave differential power amplifier using on-chip transformer is proposed to achieve high saturated power. To realize the high freqency operation, cross couple capatitor MOSFET is applied. The parasitic element is reduce the performance of the circuit. In this paper on-chip transformer is used as balun and impedance-matching network. The component loss is reduced by unifying the function...
A 50∼67 GHz double-balanced mixer for direct up-conversion using standard 90 nm CMOS technology is reported. The up-conversion mixer comprises an enhanced double-balanced Gilbert cell with current injection for power consumption reduction, and negative resistance compensation for conversion gain (CG) enhancement, a parallel and differential IF transconductance stage for bandwidth and linearity enhancement,...
An ultra-wideband (UWB) low noise amplifier (LNA) was designed and fabricated using 0.18μm 1.8V CMOS technology. The adoption of forward body biases (FBB) in a 3-stage distributed amplifier enables an aggressive scaling of the supply voltages and gate input voltage to 0.6V. The low voltage feature from FBB leads to more than 50% power consumption saving to 4.2mW. The measured power gain (S21) is higher...
This paper presents an ultra low voltage (ULV), ultra low power (ULP) and ultra wideband CMOS low noise amplifier with noise cancelling. A design methodology for optimizing the trade-off between power consumption and RF performance for a MOS transistor is employed. A current-reuse technique is used to lower the power consumption, and an inductive gm-boosting technique is exploited to increase the...
The low-noise amplifier (LNA) is used for an ultra-wideband (UWB) application. The UWB common gate LNA is designed using standard 0.18 um CMOS technology. Because of the common gate configuration, broadband input matching is obtained and the noise does not increase rapidly at higher frequencies. Bulk bias is designed for low-voltage supply through the first stage of amplification. The LNA showed the...
A 3.1–10.6GHz 1.2V supply voltage low power consumption LNA for UWB systems is presented in this paper. The proposed LNA uses common-gate (CG) LNA to make good input matching to 50Ω without an extra input-matching network. A current-reused architecture is employed to decrease the power consumption. The proposed LNA is simulated with TSMC 0.18µm 1P6M CMOS process. The max gain is 14.25dB. The input...
This paper presents a 65 GHz LC-VCO dedicated to wireless high data rate applications. It is designed in a 65nm CMOS SOI process. The proposed VCO achieves a frequency tuning range (FTR) of some 9.7% and a phase noise of −111 dBc/Hz at 10 MHz of the carrier. The power consumption is 1.1 mW when biased with a 0.8 V power supply. The silicon footprint of the VCO core is only 0.047 mm2.
This study presents a 3–10 GHz ultra-wideband low noise amplifier (UWB LNA) with an interstage technique, featuring low power consumption, high gain (S21), and a low noise figure (NF). The low power consumption UWB LNA is designed using standard 0.18µm CMOS technology. Using the interstage technique (current reused topology with a peaking inductor) achieves low power consumption. The LNA achieves...
This paper presents a 3–9 GHz CMOS low noise amplifier (LNA) designed in a 0.18 μm CMOS technology which uses negative feedback with magnetic coupling at the input of a common source-LNA instead of resistive feedback. Using the proposed topology, power gain of 14.1±1 dB and noise figure between 2.24–2.45 dB was achieved in a bandwidth (BW) of 3–9 GHz. The total drawn power of the proposed circuit...
This paper presents an Ultra-Wideband (UWB) Low-Noise Amplifier (LNA) which its frequency range is from 3.1 to 10.6 GHz using 0.18-μm CMOS at 25°C. Simulation results show that the IIP3 is about 1dBm at 6GH and the Noise Figure (NF) ranges from 3.41–4.47 dB over the band of interest. Input matching is better than −12.81dB, S12 below −27.51 dB, S22 below −13.05 dB, S21 10.16 ± 1 and the power consume...
Two K-band low-IF receivers, a single channel receiver and a quadrature receiver, are designed and fabricated in a 130 nm CMOS process. It is demonstrated that, with the proposed polyphase filter, the quadrature receiver is able to achieve similar performance as the single channel receiver in various aspects while maintaining the advantages of quadrature scheme. The measured performance of the single...
The development of Wireless Body Area Network (WBAN) is a key point enabling the mobility health. Among the most critical constrains in WBAN implementation is the power consumption of wireless featuring nodes. This work focuses on the development of ultra low power radio building blocks dedicated to 2.4 GHz ISM band. A novel design approach based on device optimization is first presented. It is then...
This paper presents the design of a CMOS RF RMS power detector for an Automatic Impedance Matching System. The power detector requirements for this application, in terms of dynamic range, resolution, settling time and power consumption, are met by distributing the dynamic range over three power detection units. The appropriate unit is dynamically selected based on the input power range. The output...
A track-and-hold (T&H) circuit has been designed and fabricated using the 65nm CMOS technology from STMicroelectronics. A fully differential architecture has been adopted. The circuit exhibits a −3dB input bandwidth wider than 8GHz. At 8GHz, the maximum sampling frequency, the measured overall power consumption and gain are 178mW and 0dB, respectively. The T&H core dissipates around 40mW....
This paper presents an ultra low power merged LNA and Mixer design for MICS (Medical Implant Communication Services) applications. A capacitor cross-coupled common gate LNA is implemented for an easy input matching and reasonable noise performance. The mixer operates in weak inversion, which significantly reduces power consumption and relaxes the voltage headroom without sacrificing the LNA performance...
In this paper, we proposed a low noise amplifier (LNA) for ultra wideband (UWB) application using TSMC 0.18μm CMOS technology. To satisfy the wide input matching, LC high-pass filter matching network is utilized in the first stage. To obtain the low power characteristic, folded-cascode with current reused technique is utilized in the second stage. The designed UWB LNA has the voltage gain of 17.6...
A tree-type 4:1 multiplexer (MUX) is designed by employing CMOS logic and eliminating impedance matching of the signal ports. The proposed circuit is realized in a 0.35-μm CMOS process. With the whole power consumption of 60 mW from a 3.3 V supply voltage, the MUX can operate at an output rate up to 3.6 Gb/s. From the measured eye-diagrams, the MUX exhibits an output voltage swing of 250 mVpp with...
In this paper, a low-power broadband automatic-gain-control (AGC) amplifier targeted for use in the Square Kilometer Array (SKA) is presented. The AGC is composed of an input power-match circuit, a linear-in-dB output variable gain amplifier (VGA), a power detector (PD), an error amplifier, a comparator and a loop filter. The input stage is power matched to 100 Ω differential source impedance, achieves...
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