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Embedded systems become part of our modern life. Most of them have real-time performance requirements that must be met for reasons of security, safety and usability. Nevertheless, someones have low performance requirements and allow simplifying the system hardware to reduce costs. In this paper, we deal with a real-time embedded system composed of one processor that executes a set of firm periodic...
Optimization of circuits to reduce power consumption is more and more important. Techniques to reduce power at architectural level are not sufficient to minimize the impact of power consumption in modern designs, using nano CMOS technologies. Classical standard cells methodology is widely used in digital designs. However it is far away of power optimization at physical design level. It is becoming...
In this paper an integer linear programming (ILP) model is proposed for identifying the optimal resources allocation and application partitioning on FPGA-based hybrid MPSoC, including the memory allocation for each processing unit and total BRAM usage on the device. The motivation behind this work is the reduction of the necessary exploration time for the identification of the optimal hybrid MPSoC...
This paper presents a fully integrated Hall sensor microsystem with a current-mode output. The system operates in open-loop and includes a Hall sensor with internal biasing, a fully differential front-end, a preamplifier chain and a voltage-to-current converter (V-I). The effects of the V-I block on the sensitivity drift of the system are analyzed and a current biasing of the Hall cells is proposed...
This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected...
An increase in vulnerability to soft errors has affected the reliability of both synchronous and asynchronous nanometer scale integrated circuits. Hence in such circuits there is a growing need to identify the soft error glitch propagation possibility before their physical design implementation. This paper proposes a new tool, the Soft Error Glitch-Propagating path Finder (SEGP-Finder), able to analyze...
This paper presents a highly-linear high-gain low noise amplifier (LNA) based on the inter stage technique. The linearized LNA is achieved by using the linear cascode amplifier as output stage utilizing a modified derivative superposition method and functionality is analyzed using Volterra series. Using simulations in 0.18μm CMOS technology, the IIP3 is improved by more than 37dBm reaching to +3dBm,...
In this study, we present an inductorless wideband low noise amplifier (LNA) for a multi-standard receiver. Adopting a gyrator-C network and a thermal noise cancelling structure with a common-drain feedback stage, a low noise figure and broadband frequency operation of an LNA were obtained. It was fabricated in a TSMC 0.18-μm CMOS process. This LNA achieved a power gain of 12 dB, a minimum noise figure...
A new DCG-FGT (Dual-Control-Gate Floating-Gate Transistor) transistor model for static and transient simulations is presented. The PSP MOS description is used as a basis for the formulation of the conduction channel behavior. The floating gate potential is implicitly computed with an added charge neutrality relation that ensures a good convergence. The model is running under electrical simulator (ELDO)...
In this paper, we analyze the compact models for carbon nanotube field-effect transistors (CNTFET) and observe that the logic-gates implemented using CNTFET with unoptimized device parameter have asymmetric voltage transfer characteristic. We propose the design of a balanced inverter circuit implemented using CNTFET devices. The proposed inverter circuit is functional over a wide range of supply voltage,...
In this paper, switch-induced error voltage of a MOS switch in a deep submicron technology, is modeled and analyzed using a continuous and physical formulation based on the EKV model. In order to show the effectiveness of this error estimation model, it has been applied to correct the DAC switch-induced error voltages in a 12-bit 1Ms/s charge-redistribution Successive Approximation (SAR) ADC. SPICE...
This paper proposes a novel complementary current approach to eliminating the code-dependence in the output impedance of current-steering digital-to-analog converters (DACs), and increasing the spurious-free dynamic range (SFDR) significantly. A 14bit 1.0GS/s current-steering DAC design example shows an SFDR increase of 10∼15dB. In traditional designs, one major effect that degrades the linearity...
This paper presents a new technique to compensate the comparator delay dispersion caused by variable input overdrive. The technique is composed of three main blocks, namely, conventional comparator, fixed delay block and variable delay block. The variable delay block is controlled such that it implements the inverse overdrive-delay characteristics of the conventional comparator. Therefore, the overall...
This paper presents a stable 4th order mismatch shaping technique using vector feedback dynamic element matching (DEM). When combined with a multi-bit sigma delta modulator, this DEM system allows high resolution band pass signals to be produced, using a low resolution unary weighted DAC.
The interest in non-synchronous design of digital circuits is growing due to technology scaling into deep submicron transistor geometries and to the problems this scaling causes to keep synchronous design advantageous. To enable most non-synchronous styles, the C-element is a fundamental device that has to be available as logic primitive. A recently proposed design flow improved a standard cell library,...
Multi-standard applications encounter several developments in the wireless systems. A single receiver is required for any standard of communication. Software Radio (SR) is an illustration of this concept. This paper presents a design methodology to ease the design of a flexible RF receiver based on an analog discrete time Fast Fourier Transform (FFT). A proposed architecture named SASP (Sampled Analog...
We introduce a new logic style called Pseudo-Static Current Mode Logic (PSCML), which aims to alleviate the power consumption and delay overhead concerns that have thwarted the wide-spread acceptance of a previously proposed Dynamic Current Mode Logic (DyCML) style. Different from DyCML, the proposed new logic style may be viewed by its environment as static, hence any PSCML-based gate/module can...
This paper introduces a framework to develop and characterize digital circuits using Carbon Nanotube Field Effect Transistors (CNFET). We define a 4-step process that involves design capture, pre-processing, circuit simulation and results extraction and interpretation. The initial work leading to this framework involves the selection of appropriate CNFET model and model parameters, and determination...
This paper describes a new architecture for Visual Simultaneous Localization And Mapping (SLAM), aimed at being implemented on different embedded boards on mobile robots. We detail the architecture of our C-coded program, which gives real-time results. We present the different methods used to get a real-time solution for the visual SLAM problem, for image processing, landmark parameterization and...
With the increase in the design complexity of MPSoC architectures and the need for more transistor/energy efficient processor architectures, designers are exploiting the parallelism at the thread level (TLP) through the implementation of embedded multithreaded processors. Moreover, future manycore architectures tend to use small footprint RISC cores. In this paper, we present a small footprint, scalar,...
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