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A 1.2 V, 10 b, 40 MS/s pipelined ADC fabricated in 0.13µm one-poly eight-metal (1P8M) standard CMOS process with MIM capacitors is presented. This ADC used a novel low-variation on-resistance CMOS sampling switch to improve the nonlinear effect and a two-stage recycling folded-cascode (RFC) amplifier with hybrid frequency compensation for power saving and low voltage supply requirements. By implementing...
A comparator-based circuit that uses switched-capacitor charging replaces the op amp in the multiplying digital-to-analog converter (MDAC) of a low-voltage algorithmic ADC. MDAC output swing beyond Vdd allows greater than rail-to-rail ADC input range. At a supply voltage of 0.55 V, the ADC achieves 8.4 bit ENOB and 1.4 Vpp differential input range. It occupies 0.65 mm2 in 0.25-μm CMOS and dissipates...
This paper presents an all-digital class-G quadrature switched-capacitor power amplifier (Q-SCPA) implemented in 65 nm CMOS. It combines in-phase (I) and quadrature (Q) signals on a shared capacitor array. The I/Q signals are digitally weighted and combined in the charge domain. Quadrature summation results in a 3 dB signal loss; Hence the Q-SCPA utilizes a class-G dual-supply architecture to improve...
In recent years, there has been an ever-increasing interest in monolithic power supplies. Integrating the power supply with the application has many direct benefits, including a reduction of the bill of materials and reduced size. Even more substantial are the potential efficiency gains due to reduced power delivery network losses and voltage margins, especially in a world dominated by energy limited...
The paper provides a deep insight to the design of an adiabatic Johnson Counter which consumes low power and delivers high performance. For achieving low power dissipation in circuits the Complementary Pass Transistor Adiabatic Logic (CPAL) is used to design the flip flops. The design of Johnson counter has been simulated and verified. The Tanner EDA tool has been used to simulate all the circuits...
A 128-bit Advanced Encryption Standard (AES) core targeted for high-performance security applications is fabricated in a 65nm CMOS technology. A novel charge-recovery logic family, called Bridge Boost Logic (BBL), is introduced in this design to achieve switching-independent energy dissipation for an intrinsic high resistance against Differential Power Analysis (DPA) attacks. Based on measurements,...
New low power dynamic MTCMOS full-adder cells have been proposed in this paper. Eight bit Domino and TSPC (True Single phase clock) adder circuits have been designed in 45 nm Multi-threshold CMOS Technology. The proposed MTCMOS dynamic adder circuits are faster as compared to static CMOS logic circuits. Due to the high-VT sleep transistor added, the leakage power of the circuits is also minimized...
We have previously proposed a new digital CMOS circuit which combined subthreshold circuit and adiabatic logic circuit with ultra-low power consumption. Our proposed circuit which is driven by two AC power supply with different frequency and amplitude, and is adapted to be provided a margin of switching timing of input signal. In this paper, we show a skew tolerance analysis of subthreshold adiabatic...
This paper presents the implementation of a Four bit Serial Input Serial Output (SISO) Shift Register using combination of Activity-Driven Optimized Clock-gating (ADOC) scheme and Run Time Power Gating (RTPG). We have proposed Activity-Driven Fine-Grained CG and RTPG integration. First, we introduce an Activity-Driven Optimized Clock-Gating scheme to improve traditional XOR-based CG. It chooses only...
Modern communication and signal processing is dependent on the high speed and low power consumption of the Analog-to-Digital converters (ADC) to a very large extent. Comparator is the basic building block of the ADCs which compares the two set of variables and change the input analog signal in digital. In this paper a new design of double tail comparator is proposed for high frequency of data conversion...
A 12-bit 60 MS/s SHA-less opamp sharing pipeline ADC utilizing switch-embedded dual-input current-reused opamp is presented in this paper. The proposed opamp sharing technique reduces the power consumption without suffering from memory effect. Two-phase overlapping clocks are proposed to ensure analog transistors in the common-mode feedback (CMFB) loop to always work in saturation thus avoiding common...
A reliable low-distortion CMOS bootstrapped sampling switch is presented. Compared to conventional bootstrapped switch, this scheme achieves more reliability because the limits of proposed circuit are VDD+VTHn and −|VTHp|. The variation of equivalent conductance of this CMOS sampling switch through input signal is alleviated by a specific switch's voltage control. The proposed switch is realized with...
A low power 10-bit successive approximation A/D converter which is designed for implantable bioelectronics is presented. The converter has a charge scaling digital-to-analog converter which also samples the input signal. The charge scaling capacitance is in a split-capacitor configuration that has a total input capacitance which is 95.5 % smaller compared to a conventional design and 25%smaller compared...
Source of power consumption for digital CMOS is analyzed and low power consumption technology of BIST for COMS VLSI is summarized in this paper. In order to reduce the internal switching activity rate of the circuit -under-test (CUT), we can recombine testing vector to raise the correlation between testing vector, an approach test pattern generation construction based on the Random Single Input Change...
A 0.39 mA 92 dB dynamic range switch-capacitor (SC) third-order ΣΔ modulator for a digital RF hearing aid in 0.35 μm CMOS is presented here. A modified-feedback topology is used here that effectively achieves a high dynamic range and the low power consumption. In the implementation, the bootstrapping-switch and the low-voltage wide-swing OTA are essentially designed for 1.2 V supply voltage with the...
This paper presents a new micro-power precision sample-and-hold (S/H) circuit for biomedical applications. In conjunction of low-power op-amp circuit design, the switched-capacitor capacitive-reset gain circuit with capacitor-mismatch compensation technique has been used. With this combination, the S/H has features of insensitive to capacitor mismatch, offset, and finite open-loop gain of op-amp whilst...
This paper presents a twice the supply voltage bootstrapped switch with the proposed rise time accelerator that has high linearity and fast rising with single phase clock input at low voltage. The proposed rise time accelerator improves rising time and ensures circuit operation at extremely low supply voltage without any complex timing generation circuit. The prototype switch is designed in 65nm CMOS...
This paper introduces new charge and discharge paths to speed up the turn-on and turn-off process of bootstrapped switch. In the mean time, linearity is improved without increasing capacitance or area. The proposed switch is designed in SMIC 65nm CMOS process and the results indicate that total harmonic distortion (THD) of 95dB is acquired when 103MHz input signal is sampled at 1Gsps.
This paper presents a new method to recover energy in an Analog-to-Digital Converter (ADC) based on the principle of adiabatic charging. The ADC comprises an Adiabatic Charging Charge Redistribution (ACCR) DAC, a dynamic comparator, and a Successive-Approximation-Register (SAR) counter. Charges in the ACCR DAC can be recovered through a resonant power supply and adiabatic switch. These charges can...
To effectively reduce output ripple of switched-capacitor DC-DC converters which generate variable output voltages, a novel feedback control scheme is presented. The proposed scheme uses pulse density and width modulation (PDWM) to reduce the output ripple with low output voltage. The prototype chip was implemented using 65nm CMOS process. The switched-capacitor DC-DC converter has 0.2-V to 0.47-V...
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