The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Power and area remain the main constraint in designing of VLSI circuits. Also, adder being one of the main components of processor design is highly researched digital module. In this paper high speed adders are designed using 130nm CMOS process and are being evaluated for their performance at lower technologies. The power dissipation, delay and area are compared for Carry select adder, ripple carry...
New low power dynamic MTCMOS full-adder cells have been proposed in this paper. Eight bit Domino and TSPC (True Single phase clock) adder circuits have been designed in 45 nm Multi-threshold CMOS Technology. The proposed MTCMOS dynamic adder circuits are faster as compared to static CMOS logic circuits. Due to the high-VT sleep transistor added, the leakage power of the circuits is also minimized...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.