The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Background
Because human fetal ventral mesencephalic tissue grafts provide promising results in ameliorating Parkinson's disease–implicated motor dysfunctions, human fetal midbrain‐derived dopamine neuronal precursor cells are considered good candidates for cell‐based therapy for Parkinson's disease in that large quantities of cells can be supplied through a good manufacturing practice–compliant...
A 2.8Gb/s all-digital CDR uses a 10b glitch-free DCO which provides a 0.2 to 0.3% frequency tuning step to reduce the quantization effect. The CDR achieves 7.2psrms jitter at 2.5Gb/s and it operates from a 0.9 to 1.2V supply. The circuit occupies 300 times 430mum2 in a 0.13mum CMOS process and dissipates 13.2mW from a 1.2V supply when operating at 2.5Gb/s.
This paper introduces jitter-boundary-based (JBB) digitally controlled de-skewing algorithm for high-speed link such as flat panel display (FPD) and memory system. It tracks data sampling points by way of finding the boundaries of jitter probability density function (JPDF). This boundary-based tracking algorithm offers lower bit error rate (BER) under the asymmetric jitter distribution as well as...
Implemented in 0.13/spl mu/m CMOS, the 40Gb/s transmitter uses shunt-and-double-series inductive peaking and negative feedback for bandwidth enhancement and pulsed latch-based dividers and retimers for timing closure. The 38.4Gb/s 2/sup 31/-1 PRBS transmitted eye has differential voltage swing of 549mV/sub pp/, rise time of 14ps, and clock jitter of 0.65/sub rms/ and 4.9/sub pp/.
An 8b 200MS/s 2.8b-per-stage pipelined ADC is realized in a 0.18/spl mu/m CMOS process. By using partially switched operational amplifiers, the ADC consumes 30mW from a 1.8V supply and occupies 0.15mm/sup 2/. The ADC achieves 47.3dB SNDR, 55.8dB SFDR, and 7.6 ENOB for a 90MHz input at 200MS/s.
A high-speed I/O circuit for the memory interface is implemented in a 0.25µm CMOS technology. To increase the sensitivity of the input circuit, the receiver employs the positive feedback. For driving of signal with the proper slew rate and specified voltage level under PVT variations, the pro-posed output circuit includes the novel level detection circuit and slew rate control scheme.
A new circuit technique named Single-Pin Driver(SPiD) is proposed. This circuit behaves like a bus terminator with negative capacitance and can be used for enhancing the switching speed of off-chip drivers, or for reducing the simultaneous switching noise by allowing smaller off-chip drivers under the same speed constraint. Experimental results show 10-50% improvement in the rise and fall times under...
A low voltage, low power CMOS delay element is proposed. With unit CMOS inverter load, the delay from 2ns to 10??s is achieved with the power consumption less than 30pW/MHz in 0.8??m CMOS technology. Based on the CMOS thyristor concept, the delay value of the proposed element can be designed in a wide range with the control current. The designed delay value is less sensitive to the supply voltage...
A serial data transmitter for ATM user-network interface is described. The data transmitter gets 8-bit parallel data from SDH processor and transmits them in a serial data stream. It uses a PLL to synthesize an 8 times faster clock than the parallel data clock, which is used for serial data transmission. To minimize bit error, the phase of the serial clock generated by the PLL is controlled by serial...
A new two-transistor memory cell concept for 16-Mbit DRAM and beyond is described. This cell offers the advantages of small cell size, non-destructive and fast operation of reading with a built-in amplifier, and the capability of storing multiple-valued or analog information.
A new high-density memory cell concept for storing analog information as well as digital data is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor generates a large bit-line signal voltage at a supply voltage as low as 1.0V. Since this cell does not need a large storage capacitance and the pass-transistor can be stacked on the top of the amplifying...
The (MI)2L structure will be discussed, which is a combination of CHL/CHIL and I2L, taking advantage of ion implantation. It provides improved speed-power product and functional density compared to conventional I2L schemes. The gate consists of a lateral npn transistor with intermediate collectors and a Schottky-inverter. The device fabrication is fully compatible with standard bipolar processes for...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.