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A 17 ns, 100 nA stand-by current, full CMOS, 1 Mbit SRAM has been developed. It was fabricated using a 0.5 um, double poly, double metal technology. The use of a full bulk CMOS 6 T memory cell allows a very low stand-by consumption. The low operating power is obtained thanks to a hierarchical architecture. A full differential data path provides a good noise immunity and a fast access time. The memory...
This paper proposes a new array architecture named extended second metal line (ESL) architecture, in which second metal line is used as not only power lines for distributed sense-amp drivers but global data-buses in the memory array. The self-recovering Vpp generator for output driver is further described to ensure the output high level in fast column access modes. By using the proposed array and...
This paper describes a high-speed D/A conversion system with an embedded 5-bit programmable FIR filtering function suitable for applications in video interfaces. For demonstration purposes a prototype chip has been fabricated in a digital 1.2 ??m single-poly CMOS technology for realizing the combined functions of an 8-bit current-steering D/A conversion and a 3-tap color carrier suppression filtering...
An ultra-high-speed error correction method for difference-set cyclic codes of longer code length has been developed that introduces pipeline architecture into the inner feedback loop of the decoding circuit and avoids the propagation of erroneous data during latency. The new architecure can in principle raise the operation speed of the error correction chip to the toggle frequency of the syndrome...
A new analog implementation of multilayer Boltzmann machines is described. Its intrinsic scalability has been achieved by original design of low-distorsion analog cells, cascadable random generators and digital interconnectios. Feasibility is demonstrated by the realization of a 1.2 GCPS unit.
The described microprocessor is a micropower multitask machine with a hardware scheduler. The task switching is performed at the instruction level. The programmer may choose a task configuration, i.e. one to four pseudo-parallel tasks depending on the application. To replace a software scheduler by a hardware scheduler allows to reduce the power consumption.
This paper presents a systematic approach to design smart-pixel chips in standard CMOS technologies. These chips include light sensors together with parallel analog signal-processing circuitry, on the same silicon substrate. Light detection is made with vertical CMOS-compatible BJTs, which yield contrasts larger by an order of magnitude than conventional photodiodes. A Darlington structure is presented...
This paper presents a programmable switched-current filter based on a universal wave filter structure which allows obtaining different filtering functions from a same low-pass reference filter, without altering the global circuit topology. A first circuit implementing a low-pass and a band-pass Chebyschev filter has been designed and fabricated in the ES2 1.5??m CMOS process. The experimentally measured...
A first order 1Hz integrated filter needing no external components is described. It uses an on-chip capacitor of 100pF and a new differential transconductance amplifier which allows direct implementation of very small transconductances by using MOS transistors in their triode region. This furthermore makes the filter cutoff frequency electrically adjustable. The distortion is very low, less than 0...
A fixed 15.5 dB gain, DC to 10 GHz transimpedance amplifier using AlGaAs / GaAs heterojunction bipolar transistor (HBT) technology is described. A 2 ??m emitter non self-aligned HBT IC Process (FT ?? 40 GHz, Fmax ?? 40 GHz) with MOCVD grown layers is used to fabricate the amplifier. The 1 dB Power compression is measured to be at 4 dBm output power. The third-order intercept point (IP3) is 19 dBm...
A 10-bit 5MS/s successive approximation ADC cell is presented. With a clock frequency of 70MHz, the sampling time is limited to 14nS, which is aimed for a parallel ADC array. A two-step principle based on unsymmetrical dualcapacitor charge-redistribution-coupling has been used. The comparator with the help of reset function presents a fast response to the successive comparison. The core of the ADC...
A controllable current amplifier with a control range of more than 60dB for application in a novel, completely integratable hearing instrument is presented. It operates on power supply voltages of 1V .. 1.3V. Low current consumption is aimed at. The maximum value is 93??A.
A low-voltage low-power bipolar automatic gain control (A.G.C.) that works in the current domain and operates on a single 1.3-V battery is presented. In this A.G.C. a large time constant (50 ms) is realised on-chip. The A.G.C. consists of a gain cell, a comparator and a voltage follower. The active circuitry of the A.G.C. has been integrated in the DIMES01 process and the total circuit demonstrates...
A CMOS circuit is presented which performs all analog interface functions to a standard telephone subscriber line including DC and AC termination, send and receive amplification, anti-side-tone network, line loss compensation, and dialing control. All transmission parameters are software programmable and are loaded into the IC during hook-off or, if necessary, during conversation. It is fabricated...
A motor control IC has been implemented for operating a small DC motor (≪5W) directly from the rectified mains using a Pulse Width Modulation (PWM) scheme. The integrated high voltage feedback loop ensures stabilization of the rotational speed at different mechanical loads in a supply range from 90-500 Vdc. The number of extermal components is reduced to those necessary for easy adjustment of relevant...
This paper presents an innovative application for analog integrated circuits, based on nonlinear signal processing concepts. We report the first monolithic realization of a chaotic continuous-time nonlinear dynamic system. It corresponds to a third order differential equation known as the Chua's equation, and has been implemented using nonlinear gm-C techniques in a 2.4??m CMOS technology. Measurements...
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