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We propose a new approach to an on-chip clock distribution scheme. It is based on distributed multi-GHz LC-tank oscillators generating local clocks. The oscillators are mutually coupled to align their frequencies and are further subharmonically injection-locked to a much lower frequency reference to align their phases. The final phase calibration is via adjusting their self-resonant frequencies. We...
This paper proposes an ultra-low-voltage (ULV) fractional-N all-digital PLL (ADPLL) powered from a single 0.5 V supply. While its DCO runs directly at 0.5 V, a switched-capacitor DC-DC converter doubles the supply voltage to all the digital circuitry and regulates the TDC supply to stabilize its resolution thus maintaining fixed inband phase noise (PN) across PVT. The ADPLL supports a 2-point modulation...
We present a new ultra-low-power (ULP) transceiver for Internet-of-Things (IoT) optimized for 28-nm CMOS. The receiver (RX) employs a high-rate (up to 10 GS/s) discrete-time (DT) architecture with intermediate frequency (IF) placed beyond the 1/f noise corner of MOS devices. New multistage multi-rate charge-sharing bandpass filters are adapted to achieve high out-of-band linearity, low noise and low...
Stacked-gate is one of the most popular solutions used in mismatch-sensitive circuits in FinFET technology. A Bandgap circuit using stacked-gate formed by 150 short-channel devices to achieve high accuracy is demonstrated. Adding uniform surrounding patterns to the target MOS array, the device mismatch caused by DGE (density gradient effect) can be cancelled. In low-power RF LNA and VCO, dc power...
This Forum is intended to provide an in-depth overview of noise modeling and simulation, and of analog, mixed-signal, and system-level solutions for low-noise sensing. State-of-the-art techniques to tackle noise in image sensors, mechanical sensors, temperature sensors, magnetic sensors and bio-sensors will be critically analyzed. The forum will explicitly address the trade-off between noise and energy...
The continuous scaling of CMOS technology increases processor performance and memory capacity, requiring the CPU/Memory interface to have ever-higher bandwidth and energy efficiency over the past few years. Among those cutting-edge interface technologies, multi-band (multi-tone) signaling has shown great potential because of its high data-rate capability along with its low energy consumption [3]–[5]...
3D stacking and computational imaging are two major driving forces for CMOS image sensors. In addition, 3D stacking separates pixel array and peripheral circuits. As such, computational imaging blocks (stereo vision, array camera, reconfigurable instruction cell array, etc.) can integrate with sensor circuits while leveraging advanced CMOS technologies including FinFET. To accommodate this trend,...
Spectra from 0.5 to 0.6THz play critical roles in planetary science, astrophysics and radio-astronomy as various chemical species including water, nitrates (NO2, N2O, NH3) and organics (CH4 and HCN) can either absorb or reflect radiation in this frequency regime. Accordingly, NASA and ESA have developed a wide range of spectroscopic sounding instruments to investigate our solar system. Current LO...
We propose a new transmitter (TX) architecture for ultra-low power radios. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during direct DCO data modulation...
A conditional correlated multiple sampling (CCMS) technique for low noise CMOS image sensor (CIS) is proposed to reduce noise and address low frame rate issue caused by the conventional correlated multiple sampling (CMS) technique. An 8Mpixel 3D-stacked CIS with 1.1um pixel pitch is designed and verified. Measurement results show this technique can achieve 0.66e−rms at 36.1 kHz A/D sampling rate per...
This paper investigates the microwave lowpass filters in integrated fan-out wafer-level packaging (InFO-WLP) technology. The Chebyshev prototype is adopted to achieve sharp cutoff at the edge of passband. A lumped-LC structure and three different distributed structures, including λ/8 stubs, stepped-impedance, and periodic tapered electromagnetic bandgap (EBG), are employed to find an appropriate microwave...
By co-design methodology, an integrated 2.4 GHz band-pass filter using grounded spiral inductors symmetrically at input/output ports for ESD protection is realized in integrated passive device (IPD) technology. With the novel input/output admittance-inverter (J-inverter) and the weakly coupled transformer, the transmission zeros can be introduced to increase the stop band attenuation. Also, the shunt...
This paper presents a monolithically integrated 2×4 coherent source array operating at 0.54–0.55 Tera-Hertz (THz) in 65nm digital CMOS technology. The source array contains 20 oscillating elements which can radiate in-phase THz signal via each of their own differential slot ring antennas. Each of the oscillating elements is made of a triple-pushed Colpitts voltage controlled oscillator (TPCVCO). Among...
The noise performance of an all-digital phase-locked loop (ADPLL) is limited by the resolution of the time-to-digital converter (TDC). Most TDC research in the past focused on the arrival time difference between the edges of the divider feedback and the reference signal [1-2]. This results in coarser TDC resolution and worse ADPLL noise performance. This paper presents a fractional-/VADPLL that employs...
A 1.1 um pitch pixel array fabricated by 45 nm 3D stacked technology, can be switched to peripheral circuits on same wafer or to other stacked wafer for process and signal integrity verification. It supports through silicon connection or direct connection to increase the flexibility by separating pixel array and sensing circuit. The novel wide operation range VCO and low power serializer are implemented...
We propose a new architecture of an all-digital PLL (ADPLL) for advanced cellular radios that is optimized for 28 nm CMOS. It is based on a wide tuning range, fine-resolution class-F DCO with only switchable metal capacitors and a phase-predictive TDC. The 8mW DCO emits −157 dBc/Hz at 20MHz offset at ∼2 GHz, while fully satisfying metal density rules. The 0.4mW TDC clocked at 40MHz achieves PVT-stabilized...
New materials and technologies are enabling next generation systems and applications. The first four papers in this session combine different semiconductor materials (organic and/or oxide) on flexible foils to realize a variety of applications such as a microprocessor, a display, a sensor and an RFID tag. Papers 5, 8 and 9 combine in a hybrid manner crystalline high-bandgap semiconductors on top of...
Next-generation high-performance computing systems require high-bandwidth serial links to transport high-speed data streams among computational blocks. Optical links have recently attracted attention due to their low channel loss at high frequencies, requiring simpler equalization circuits than electrical links. The energy-efficiency of optical links can thus be significantly improved [1-5]. Broadband...
This study presents a 53.6 GHz wideband direct injection-locked frequency divider (DILFD) using 65 nm CMOS technology. By operating a RF input transistor in subthreshold region and changing its forward body bias, the proposed DILFD achieves a 28.6 GHz (72%) locking range with 6.7 mW power consumption and 1 V supply voltage. When varying the supply voltage from 0.9 V to 1.1 V or its physical temperature...
With continuing technology scaling, enabling advances in computation, memory, and communication, energy-efficient memory and wireless communication will become even more important for ubiquitous mobility. This session introduces several emerging memory and wireless technologies enabling improved energy efficiency. Integration of non-volatile memory with logic for data retention, integration of a timing...
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