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A unique gate stack solution has been found in gate-first FDSOI to meet at the same time high performance, low leakage, VT centering and reliability criteria for NMOS and PMOS with Tinv=12.5Å and 14Å, respectively. Trade-offs between those characteristics are highlighted in this paper through process knob variations, including the interfacial layer (IL) formation, the IL surface treatment and the...
We propose and demonstrate a new low power phase change memory using a novel 3D network of crystallites with phase change confined to only at grain intersections. Contrary to conventional phase change memories, for which an entire volume of chalcogenide glass is amorphized or crystallized for high or low resistance, we propose a multi-grained structure where we only induce phase change in the inter-grain...
We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. “STRASS” and “BOX creep” techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-the-art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process...
SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1–4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1–4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In...
12″ manufacturable 90nm CMOS fully compatible 1Mb HfO2-ReRAM by 2 extra masks between Metals with BEoL thermal stress immunity is for the first time achieved in this work. Cycle random soft error, for the first time systematically observed in this work, due to improper phase-transition of TiOδ on filament are successfully suppressed by stoichiometric engineering on HfO2 / reservoir interface to achieve...
For the first time, two different types of electron traps are clearly identified in Ge nFETs with Type-A controlled by the HfO2 layer thickness and Type-B by the Si growth induced Ge segregation. Only Type-B are responsible for mobility degradation and they do not saturate with stress time, while the opposite applies to Type A. A PBTI model is proposed and validated for the long term prediction.
Novel crossbar antifuse for high-density user programmable logic array (PLA) is presented. Circuit area reduction and routability increase of PLA are achieved by crossbar architecture based on pure-CMOS antifuse adjacently integrated into low-voltage and high-speed logic transistors. In addition, since our crossbar antifuse technique can be fabricated according to the standard design rule of advanced...
We demonstrate a technique for selective GeOx-scavenging which creates a GeOx-free IL on Si1−xGex substrates. This process reduces Nit by >60% to 2e11 and increases high-field mobility at Ninv=1e13 cm−2 by ∼1.3× in Si0.6Ge0.4 pFETs with sub-nm EOT.
Sub-30nm LG Fin-replacement strained-Germanium pFinFETs at state-of-art device dimensions are reported with optimized S/D junctions and RMG stack. Competitive performance is shown for the first time when comparing the sGe devices with counterparts from the same 14–16nm R&D platform (Ge vs Si channel, FinFET vs lateral Gate All around). Improvement in channel passivation efficiency at scaled device...
In this work, we report a ferroelectric versatile memory (FE-VM) with strained-gate engineering. The memory window of high strain case was improved by ∼47% at the same ferroelectric thickness, which agrees with the increase of orthorhombic crystallinity. Based on a reliable first principle calculation (FPC), we clarify that the gate strain accelerates the phase transformation from metastable monoclinic...
In0.53Ga0.47As quantum-well (QW) MOSFETs with a novel interfacial layer(IL)/high-k stack on an improved interface were fabricated. Excellent device characteristics (SS∼72mV/dec, Ion/Ioff>106 at Vds=0.5V, DIBL∼26mV/v for a device at EOT∼1.25nm) were obtained. In addition, EOT was scaled down to 1.0 nm without a significant degradation in electrical properties. The extracted field-effect mobility...
We report a record-setting low NMOS contact resistivity of 1.2×10−9 Ωcm2 compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as...
We report significant improvement of the TiSi / p-SiGe contact resistance by using a cryogenic (cold) boron implantation technique inside the contact trench of FinFET devices, providing both a source of dopants and a localized amorphization of the source/drain, self-aligned on the contact trench. A record low p-type contact resistivity of 5.9×10−9 ohm-cm2 is demonstrated and a 7.5% performance improvement...
A fast charge loss within a few seconds, which is referred to as early retention, was observed in tube-type 2y word-line stacked 3-D NAND flash memory for the first time, and the origin of the early retention was comprehensively evaluated. Using a fast-response pulse I–V system, the early retention characteristics from microseconds to seconds were thoroughly investigated, and the correlations with...
We report the first quantum bit (qubit) device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot (QD) defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate...
In low cost vertical resistive switching memory (VRRAM), the inter-layer leakage becomes a serious problem, primarily resulting from the ultimate scaling in the vertical dimension. In this work, for the first time, we present a novel approach of fabricating 3D VRRAM using self-aligned self-selective RRAM to effectively address such challenge. By successfully suppressing the inter-layer leakage, the...
We demonstrate an advanced a-VMCO nonfilamentary resistive switching memory cell with self-rectifying, self-compliant, forming-free and analog behavior. A BEOL-compatible process yields devices with excellent device-to-device variability, down to 40nm size. Detailed analysis of the a-Si/TiO2 interface enables understanding the barrier resistance modulation, engineered for wider on/off window and current...
In this work, a design-technology co-optimization (DTCO) platform for 7nm node nanowire and beyond is demonstrated for the first time. The platform extends from predictive TCAD simulations through compact model extraction to circuit simulation. The impact of different cross-section geometries, design of experiment, parasitic effects, global variation and local variation are accurately and efficiently...
We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be directly induced by the strain in the SiGe channel and reproduced by an accurate electrical compact model. An original continuous-RX design optimizes the stress management, maintaining longitudinal...
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