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Modular polynomial multiplication is the most computationally intensive operation in many homomorphic encryption schemes. In order to accelerate homomorphic computations, we propose a software/hardware (SW/HW) co-designed accelerator integrating fast software algorithms with a configurable hardware polynomial multiplier. The hardware accelerator is implemented through a High-Level Synthesis (HLS)...
Control-flow checking (CFC) is one of the main approaches to monitor the behavior of a microprocessor-based system without specific assumptions on error models (e.g., single bit flips). Many approaches have been proposed and evaluated, but none takes explicitly into account the possibility of indirect jumps or calls for which destination addresses are not hard-coded. This paper discusses first the...
In the era of the cloud computing, homomorphic encryption allows remote data processing while preserving confidentiality. Its main drawback, however, is the huge complexity in terms of operand size and computation time, which makes hardware acceleration desirable in order to achieve acceptable performance. In this paper, we present a flexible modular polynomial multiplier implemented through a high-level...
Design-time evaluations of the sensitivity of circuits with respect to soft errors are usually done by means of fault injection campaigns. Such campaigns are time-consuming, either in order to prepare the hardware set-up (e.g., prototype on emulation platform) or in terms of simulation run. We propose here an approach avoiding any fault injections but able to evaluate the intrinsic sensitivity of...
Evaluating the robustness of circuits with respect to soft errors has become of utmost importance in many application areas. This evaluation must in most cases be refined taking into account the application characteristics in order to avoid too pessimistic results. The main approach used today at design time is based on fault injection campaigns. Emulation can be used to speed up the evaluations,...
Circuits with security constraints must be protected against hardware attacks, including laser-based perturbations. Early evaluations at design time are required to avoid costly and time consuming modifications that might be required after actual laser attacks on the first prototypes. Such evaluations include fault injection compaigns from RTL descriptions. The accuracy of the results depends on the...
Fully Homomorphic Encryption (FHE) becomes an important encryption scheme in the frame of Cloud computing. Current software implementations are however very slow and require a huge computing power. This work investigates the possibility to accelerate FHE by implementing it in off-the-shelf FPGAs. The focus is on one critical function in the FHE scheme: the polynomial multiplication. In this paper,...
Embedded software is at the heart of many systems, including critical ones. It is therefore often mandatory to precisely identify, for a given application, the robustness level achieved with respect to various perturbations. This paper is focused on soft errors occurring in internal registers of pipelined processors. Two criticality evaluation approaches are compared; one based on criteria evaluated...
The probability of application failures due to soft errors in microprocessors is directly related to the lifetime of data stored in the internal registers. For high performance processors, the accurate analysis of this lifetime is difficult due to the various micro-architecture features, including pipeline registers and fast-forwarding connections managing data dependencies. Using fault injections...
Lasers have become one of the most efficient means to attack secure integrated systems. Actual faults or errors induced in the system depend on many parameters, including the circuit technology and the laser characteristics. Understanding the physical effects is mandatory to correctly evaluate during the design flow the potential consequences of a laser-based attack and implement efficient counter-measures...
Implementation attacks are a major threat to hardware cryptographic implementations. These attacks exploit the correlation existing between the computed data and variables such as computation time, consumed power, and electromagnetic (EM) emissions. Recently, the EM channel has been proven as an effective passive and active attack technique against secure implementations. In this paper, we resume...
Evaluating early at design time the level of security achieved with respect to fault-based hardware attacks requires understanding and accurately modeling the faults that can actually occur in a circuit under attack. Attacks with lasers can produce single or multiple-bit errors, while having a local impact in the circuit. This paper discusses several fault or error models that can be considered at...
Soft errors with multiple erroneous bits have become a significant threat in embedded systems. New approaches must therefore be proposed to detect errors in a system without assumptions on the error multiplicity. Behavioral checking is in that case appealing. This paper presents a new extended and flexible control flow error detection approach, able to also cover errors in the critical variables of...
Soft errors in the configuration memory of SRAM-based FPGAs cause significant and remanent application disturbances. However, classical mitigation techniques based on massive redundancy are too costly for most applications. The method presented in this paper is based on selective redundancy in partially used LUTs. It can be applied so that no hardware is added at the system level and it has been automated...
Side-channel analysis is one of the most efficient techniques available to an attacker to break the security of a cryptographic device. Started as monitoring of computation time or power, it has evolved into considering several other possible information leakage sources, such as electromagnetic (EM) emissions. EM waves can be a very attractive means to attack a cryptographic implementation: they are...
Product or design quality encompasses many aspects. One of them is the robustness with respect to perturbations. This robustness depends on the implementation technology, but can also be improved at design time. This paper is focused on designs implemented in SRAM-based FPGAs that are sensitive to soft errors in the configuration memory. An approach is proposed to increase the dependability with respect...
Soft errors in the configuration memory of SRAM-based FPGAs cause significant application disturbances. We demonstrate on Xilinx and Altera FPGAs the feasibility of a very low cost and automated mitigation approach and we evaluate its efficiency.
Several criteria can be used to evaluate the criticality of registers and memory locations at compile time. This evaluation is useful to guide optimizations with respect to robustness constraints and soft error mitigation. In this paper, we analyze in detail the impact of compilation optimizations on the system dependability, using four different criteria. We show that optimizations enabled by default...
Several criteria can be used to assess the criticality of registers or variables at compile time and to guide software optimization with respect to robustness constraints. On the basis of such criteria, we analyze in detail the impact of compilation optimizations on the system dependability. We show that optimizations enabled by default lead to criticality increase. However, selectively picking optimizations...
Multiple errors are an increasing concern for designers. Multiple errors in the configuration memory have to be taken into account when a circuit is implemented on a SRAM-based FPGA. This paper reports on the impact of realistic multiple-bit errors in the configuration, with respect to the robustness of a processor with error detection mechanisms.
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