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This work presents a rad-hard 4-bit 10MHz Flash ADC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels. The design takes into account the different effects of the radiation that could damage the circuits in harsh environments. The ADC has been integrated in a standard CMOS 0.18-μm technology by TowerJazz. The prototype has...
To mitigate the higher noise figure (NF) of CMOS-based subharmonic mixers (SHMs) relative to their diode-based counterparts, this paper proposes the use of a low-noise transconductance amplifier (LNTA) ahead of the mixing core. The LNTA has a noise-cancelling topology that enables the mixer to have a high conversion gain and low NF over the RF input band of 4.5 GHz to 8.5 GHz. A chip was fabricated...
This paper presents an energy-efficient forwarded-clock receiver in 40nm CMOS process. The receiver adopts injection-locked ring oscillator (ILRO) to implement jitter filtering and phase deskew. The proposed cascaded ILROs enable our receiver to maintain a constant jitter tracking bandwidth (JTB) for good jitter tolerance and generate accurate quadrature clocks for quarter-rate sampling. The first-stage...
This paper demonstrates that it is possible to demodulate a RF signal composed of four aggregated frequency bands by a single demodulator, named "Three Phase Demodulator (TPD)". Measurements results will be analyzed in the case of 4 carriers modulated by two different modulation formats (QPSK and 16-QAM). The bandwidth of each modulated signal is 5 MHz and offers an overall bit rate of 128...
This paper presents novel approaches to design and validation of a secure hardware Random Number Generator (RNG), Filtered-FCSR cascade, which is based upon the structure of Gollmann cascade. To further validate the security of the proposed RNG structure a more extensive check has been performed over many output bit sequences, using the US National Institute of Standard and Technology (NIST) SP 800–22...
An all-digital reconfigurable (10-to-16-bit) sensor ADC based on TAD (Time A/D converter) is completely digital, using a ring-delay-line RDL driven by an input voltage Vin as its power supply. This method realized 16.2bit/100ksps/37.5nW from 0.6V supply without any static current using a 0.016mm2 prototype 4CKES (4-clock-edge-shift) TAD in a 65nm digital CMOS. Resolutions can be controlled by setting...
We propose a Digial-to-Time Converter (DTC) that is capable of providing infinite-delay-over-time for application in low-jitter digital phase locked loops. The DTC is implemented using phase interpolation of quadrature phase high-speed clock signals with weight coefficients generated by direct digital synthesis. Novelty of the architecture lies in using (i) a slow-settling current steering DAC that...
This paper presents a 1–6-GHz scalable microradio receiver unit that can be used in radiation pattern measurement. With no mechanical movement or manual adjustment, the measuring environment with the scalable microradio receiver substantially enhances the degrees of freedom and reduces the cost and time in radiation pattern measurement. Implemented in a 90-nm CMOS technology supporting a 1–6-GHz frequency...
A new variant of Class-EF power amplifier (PA), the so-called third-harmonic-peaking Class-EF, is presented. It inherits a soft-switching operation from the Class-E PA and a low peak switch voltage from the Class-F PA. More importantly, the new topology allows operations at higher frequencies and permits deployment of large transistors which is normally prohibited since they are always accompanied...
This paper presents a wideband inductorless Balun-LNA targeting spin torque oscillator-based magnetic field sensing applications. The LNA consists of a CS stage combined with a cross-coupled CG stage, which offers wideband matching, noise/distortion cancellation and gain boosting, simultaneously. The Balun-LNA is implemented in a 65 nm CMOS technology, and it is fully ESD-protected and packaged. Measurement...
Complex arithmetic operations are widely used in Digital Signal Processing (DSP) applications. Targeting to increase performance, in this work, we focus on optimizing the design of the modulo 2n − 1 Add-Multiply (AM) operation. We incorporate in the design the direct recoding of the sum of two numbers in its Modified Booth (MB) form. Compared to the conventional design of first instantiating a modulo...
Adaptive time step control is very important or even crucial in transient simulation for the efficiency of a circuit simulator. Existing methods are mainly based on the formula of the local truncation error (LTE) for solving ordinary differential equations (ODEs), which is an approximation for the circuit simulator solving a system of nonlinear differential algebraic equations (DAEs). In this work,...
In this paper, a low-noise CMOS Image Sensor (CIS) based on a 14-bit Two-Step Single-Slope ADC (TS SS ADC) and a column self-calibration technique is proposed. The TS SS ADC is good for the video system which requires fast operation because its conversion speed is faster than the Single Slope ADC (SS ADC) by more than 10 times. However, there are a lot of errors in the circuit operation on the connection...
A low power Fast Ethernet line driver has been designed in a 180 nm CMOS technology from XFAB. A very low power consumption is achieved with class-B operation. Due to incorporating digital-to-analog conversion to the line driver itself, the power consumption could be further reduced. The power consumption in transmit mode is minimized to 38 mW, which is the lowest one of previous reported line drivers...
This paper presents a new Zero-Crossing Digital Phase-Locked Loop (ZC-DPLL) for frequency synchronization and tracking. The proposed hyperbolic Σ-Δ based ZC-DPLL has an improved time jitter by a factor of 6.4 and an extended lock-in range by a factor of sinh(π)/π. These significant improvements were achieved by introducing a hyperbolic nonlinearity and a modified Σ-Δ blocks to the original ZC-DPLL...
This paper presents a low-power optimization technique (LPOT) for a 1V pipelined RISC microprocessor circuit via multi-threshold CMOS (MTCMOS) techniques. Using the MTCMOS LPOT, a 32-bit pipelined RISC microprocessor test circuit having 144,000 transistors with 3 stages per instruction has been optimized in terms of power consumption using standard threshold-SVT and high threshold-HVT logic cells...
Current-mode circuits are generally desirable for their high bandwidth. Moreover, current-mode instrumentation amplifiers have an advantage over voltage-mode counterparts that, they do not require precise resistor matching for a high CMRR. In this work, a current-mode instrumentation amplifier is proposed by employing Differential Difference Current Conveyor (DDCC). The proposed structure employs...
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