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This paper presents a novel subthreshold 8T-SRAM for ultra-low power applications. The proposed SRAM cell improves write margin by at least 22% to the standard 6T-SRAM cell at supply voltage of 1V compared. Furthermore, read static noise margin is improved by at least 2.2X compared to the standard 6T-SRAM cell. Although by the use of the proposed SRAM cell, the total leakage power is increased for...
In recent technology nodes, it has been observed that the leakage current component due to Gate Induced Drain Leakage (GIDL) is a significant contributor towards the overall standby leakage. The circuit proposed in this paper reduces the GIDL current and hence the overall standby power in CMOS output buffers by a factor of ~5.5X. Further, speed of operation of the circuitry is not compromised in the...
VLIW architectures are widely employed in several embedded signal applications since they offer the opportunity to obtain high computational performances while maintaining reduced clock rate and power consumption. Recently, VLIW processors are being considered for employment in various embedded processing systems, including safety-critical ones (e.g., in the aerospace, automotive and rail transport...
This paper compares the proposed technique with various MATLAB-built-in deconvolution-functions with regard to deconvolution errors, which have a crucial impact in reversing the effects of convolution with Random Telegraph Noise (RTN) on overall SRAM margin variations. The proposed technique successfully circumvents the issue of ringing error thanks to eliminating the need for any operations of differential,...
This paper presents a combined solution to the Through-Silicon-Via (TSV) placement and mapping of cores to routers in a three-dimensional Network-on-Chip (NoC) design. It takes care of TSV geometries and communication requirements between cores. Comparison has been carried out with the recent 3D mapping results. Both static and dynamic performance have been considered. It shows that an intelligent...
Prior work demonstrated the use of specialized pro-cessors, or accelerators, be energy-efficient for binary floating-point (BFP) division and square root, and for decimal floating-point (DFP) operations. In the dark silicon era, where not all the circuits on the die can be powered simultaneously, we propose a hybrid BFP/DFP engine to perform BFP division and DFP addition, multiplication and division...
This paper proposes a technique for reducing energy consumed by hybrid caches that have both SRAM and STT-RAM (Spin-Transfer Torque RAM) in multi-core architecture. It is based on dynamic partitioning of the SRAM cache as well as the STT-RAM cache. It assigns cache blocks to a specific region of a cache based on an existing technique called read-write aware region-based hybrid cache architecture....
Microfluidic large-scale integration (mLSI) chips comprise hundreds or thousands of microvalves integrated into a chemically inert elastomeric substrate. The design of these chips is time-consuming, error-prone, and presently performed by hand. To enhance design automation, a routability-oriented placement algorithm based on simulated annealing is introduced. This paper investigates relevant issues...
A highly efficient test compression scheme for 3D-ICs is proposed, which uses sequential linear decompressors local to each core. The compressed test data is brought from the tester over the test access mechanism (TAM) to the cores where they are decompressed. The idea is to provide flexibility in the utilization of the free variables (i.e., bits stored on the tester that can be assigned 0 or 1),...
Validation of an embedded test technique in terms of its expected yield loss and test escape metrics is a key step before it can be deployed in high-volume manufacturing. However, performing this validation at the design stage usually demands extensive computational resources, which may render electrical simulations infeasible. In this paper, we propose a digital test technique for dynamic test of...
We discuss about logic synthesis and formal verification of combinational circuits mapped to a given fixed topology. Here “fixed topology” means that circuit structures in terms of net lists except for gate/cell types are fixed in advance. That is, for logic synthesis, what should be generated are the types of gates/cells (or simply gates) in the circuits, and all the others are prefixed before synthesis...
Several approaches have been proposed for cosimulation between QEMU and SystemC. On the contrary, no paper addresses integration between Open Virtual Platform (OVP) and SystemC. Indeed, OVP models and the related simulator can be integrated into SystemC designs by using TLM 2.0 wrappers and opportune OVP APIs. However, this solution presents some disadvantages, like the incapability of supporting...
A new layered reconfigurable architecture is proposed which exploits modularity, scalability and flexibility to achieve high energy efficiency and memory bandwidth. Using two flavors of Column-wise Givens rotation, derived from traditional Fast Givens and Square root and Division Free Givens Rotation algorithms the architecture is thoroughly evaluated for scalability, speed, area and energy. Combining...
This paper presents design rule checking (DRC) methods to address challenges caused by non-Manhattan geometries that are widely present in photonic integrated circuit (PIC) physical designs. Verifying such layouts with traditional DRC tools results in a huge number of false errors that are impossible to debug; and some physical rules are simply uncheckable. We demonstrate the use of an extended DRC...
Low leakage input vector determination in data path intensive circuits is often not feasible through exhaustive simulation. Hence, top down interval propagation technique for low leakage vector determination is proposed in this paper. This technique is a variation to the heuristic used in [1]. For each RTL module, several low leakage intervals are identified. As the module size increases, exhaustive...
Complex Systems on Chips (SoCs) are built by assembling hardware and software components. SystemC TLM (Transaction Level Modeling) allows to describe SoCs in a very abstract way. From this level, a typical design flow enables the definition of virtual prototypes at different levels of abstraction to support early software development and verification of hardware blocks which, in the last steps, become...
In on-chip interconnection networks, performance optimization techniques can be often achieved in two opposite ways: by making control logic more complex inside switches, or by pushing design complexity to the switch boundaries. The implementation of virtual channel (VC) flow control is an important application domain of this design trade-off. The data path of VC switches typically exhibits replicated...
In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to 1) reduce the memory and core power consumption; 2) provide higher bandwidth. Firstly, a memory die is designed and staked with MEP die. By adding face-to-face (F2F) pad and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D...
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