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Two fully integrated low noise amplifiers using gm-boosting technique for ultra-low voltage and ultra-low-power GPS applications are designed and simulated in a standard 0.18µm CMOS technology. By employing the folded cascode and forward body bias technique, the proposed LNAs can operate at reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 17.6 dB with a...
An ultra-low-voltage ultra-low-power operational transconductance amplifier (OTA) using dynamic threshold MOS (DTMOS) technique is presented in this paper. The proposed topology is based on a bulk and gate driven input differential pair employs a gain-stage in the Miller capacitor feedback path to improve the pole-splitting effect. The circuit is designed in the 0.18µm CMOS technology. The simulation...
This paper presents a highly-linear, low power, low noise amplifier (LNA) using a novel nonlinearity cancellation technique by employing the folded cascode topology. The circuit functionality is analyzed using Volterra series analysis. The linear LNA was designed and simulated in a TSMC 0.18µm CMOS process at 5GHz frequency. By employing the new technique, the IIP3 is improved by more than 14dB compare...
A fully integrated low noise amplifier suitable for ultra-low voltage and ultra-low-power UWB applications is designed and simulated in a standard 0.18µm CMOS technology. Using the common gate, current reuse topology and forward body biasing technique, the proposed UWB LNA works at a very low supply voltage and low power consumption. The flat gain diagram of the LNA are achieved by the series inductors...
Design and simulated results of a fully integrated 5GHz CMOS LNAs are presented. To design these LNAs, the parasitic input resistance of a MOSFET is converted to 50Ω by a simple L-C network, hence eliminating the need for source degeneration. As it is analytically shown, this is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET's input resistance...
A new fully differential ultra low-voltage, ultra low-power down-converter mixer for ultra wideband application is presented in this paper. This mixer is designed using four-terminal MOS transistors. The radio frequency is applied to source and local-oscillator signal is applied to the gate with body of devices simultaneously. A DTMOS common source amplifier is employed increasing conversion gain...
This paper presents a fast and accurate method for extracting the scattering parameters of a RF MEMS switch by using its essential parameters. A neural network is developed for parametric modeling of the switch. The essential parameters of the switch are analyzed in terms of its return loss and isolation with variation of its geometrical component values. Simulation results show that the proposed...
All oscillators are periodically time varying systems, so to accurate phase noise calculation and simulation, time varying model should be considered. Phase noise is an important characteristic of oscillator design. It defined as the spectral density of the oscillator spectrum at an offset from the center frequency of the oscillator relative to the power of the oscillator. In this paper we study linear...
This paper presents a highly-linear high-gain low noise amplifier (LNA) based on the inter stage technique. The linearized LNA is achieved by using the linear cascode amplifier as output stage utilizing a modified derivative superposition method and functionality is analyzed using Volterra series. Using simulations in 0.18μm CMOS technology, the IIP3 is improved by more than 37dBm reaching to +3dBm,...
A highly efficient fully integrated passive CMOS rectifier is proposed in this paper. Using four ultra low power and low voltage techniques with proper leakage current compensation technique, this new topology is very high efficient in wide input voltage range of both high voltages and low voltage advanced sub-micron applications simultaneously. In 0.5V AC input signal amplitude the power and voltage...
In this paper, we propose a novel 1-bit full adder using hybrid-CMOS logic style. The new full adder is based on a novel XOR-XNOR circuit that generates XOR and XNOR full-swing outputs simultaneously and outperforms its best counterpart showing 28% improvement in power-delay product (PDP). Design of proposed full adder is based on improvement in the PDP and it provides full-swing output with good...
A fully differential ultra low-voltage, ultra low-power down-conversion mixer is presented in this paper. The mixer is designed using four-terminal MOS transistors. The radio-frequency (RF) and local-oscillator signals are applied to the gate and bulk of the devices, respectively. The proposed circuit is designed and simulated in the TSMC 0.18_µm CMOS process, with a 1.9GHz RF signal; the simulation...
A fully integrated 1.5 GHz low noise amplifier suitable for ultra-low voltage applications is designed and simulated in a standard 0.18µm CMOS technology. Using the folded cascode topology and forward body biasing technique, the proposed LNA works at a very low supply voltage and low power consumption. The proposed LNA has a power gain (S21) of 22 dB with a noise figure of 1.9 dB, while consuming...
A fully integrated low noise amplifier suitable for ultra-low voltage and ultra-low-power GPS applications is designed and simulated in a standard 0.18μm CMOS technology. By employing the folded cascode and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 17.6 dB with a noise figure of 3 dB,...
A fully integrated low noise amplifier suitable for ultra-low voltage and ultra-low-power GPS applications is designed and simulated in a standard 0.18μm CMOS technology. By employing the folded cascode and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 17.6 dB with a noise figure of 3 dB,...
This paper presents an analysis of phase noise in LC oscillators, and simulation results for CMOS quadrature-voltage-controlled-oscillator (QVCO) working in the 1.5-GHz frequency range. The phase noise data for a proposed BG-QVCO (-141 dBc/Hz at 1 MHz frequency offset from the carrier, for a power consumption of 5.4 mW). The noise of the coupling transistor is identified, and relationship between...
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