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This paper presents a comparative study of 2.4 GHz double-balanced Gilbert mixers with devices operating in both weak and strong inversion. The current drawn from the supply voltage by the mixers in both weak and strong inversion is chosen to be less than 100 µA through proper biasing and sizing. Two Gilbert mixers are designed in IBM CMRF8SF-0.13µm 1.2V CMOS technology and analyzed using Spectre...
Scratchpad memories have been shown to reduce power consumption, but the different characteristics of nanometer scale processes such as increased leakage power motivate an examination of how the benefits of these memories change with process scaling. Awareness of process trends and application characteristics can help designers predict the energy savings likely to result from the use of a scratchpad...
This paper presents new approaches for realizing high quality factor continuous-time asymmetric-slope second-order band-pass filters based on concepts of fractional-order filters. Two non-conventional transfer functions and two possible circuits, one based on a floating Frequency Dependent Negative Resistor (FDNR) and one based on a floating inductor both using a fractional capacitor, are proposed...
A 4 Gb DRAM architecture utilizing a scalable number of data pins is proposed. The architecture does not impact chip size and does not require additional metal layers. The 4 Gb DRAM measure 68.88 mm2 and achieves an array efficiency of 59.9%. This was accomplished by using a split bank, edge I/O interface, central row, and central column structures. The architecture coincides with the chip size and...
Modern collections of algorithms for DSP and multimedia often rely on linear algebra operators to perform massive numerical transformations on vectorized data. Embedded developers often experience the worst condition of having no FPU at all in their low-power systems, as many device producers consider FP-math as an expensive option in terms of gates and power consumption. Main aim of this work is...
In this two-part paper, we present an efficient approach for the implementation of delayed least mean square (DLMS) adaptive filter. To have satisfactory convergence performance of DLMS algorithm, we have reduced the adaptation delay and at the same time we have also reduced the critical path to support high input-sampling rate. For achieving lower adaptation-delay and to have area-delay-power efficient...
In the first part of this paper, we have discussed our proposed scheme to realize delayed least mean square (DLMS) adaptive filter with low-adaptation delay to have better convergence performance and to maintain small critical path to support high input sampling rate. Besides, we have proposed a novel multiplication cell for efficient implementation of error estimation block and weight update block...
A power amplifier, a phase shifter, a digital attenuator, and a transmit/receive (T/R) switch are fabricated for X-band phased array applications, which are implemented with CMOS 0.18 um technology. The power amplifier has 2-stage differential and cascode structures. It provides 1-dB gain-compressed output power (P1dB) of 20 dBm and power-added-efficiency (PAE) of 19 % at 8–11 GHz frequencies. The...
A dual-mode power amplifier is designed in 65nm CMOS technology to have high efficiency at power back-off. It consists of two branches, one branch is a two-stage class A amplifier and the other is a three-stage class C amplifier. This amplifier has two different modes of operation at power back-off and at peak power. The main design issues for having high efficiency at output power back-off are discussed...
Time-interleaving several Analog to Digital Converters (ADC) is considered as efficient solution to significantly increase the sampling rate. Unfortunately, due to the manufacturing process, static errors in Time-Interleaved Analog to Digital Converter (TIADC) often generate undesirable spurs which reduce the TIADC effective resolution. In this paper we propose a new blind and online digital calibration...
This paper presents a novel high-gain CMOS amplifier suitable for ultra-wideband (UWB) applications. The proposed amplifier achieves a -3 dB bandwidth covering the entire FCC UWB spectrum from 3.1 GHz to 10.6 GHz with a very high gain of approximately 70 dB. The amplifier is an area-efficient, single-inductor solution designed for TSMC 90 nm CMOS low-power process while consuming 25.1 mW from 1.2...
High resolution video (720p, 1080i and 1080p frame sizes, up to 60 fps), even if widespread in prosumer/consumer markets, still represents an absolute challenge in the embedded and low power devices, especially due to the increasing complexity of compression schemes. H.264/AVC represents actual de facto standard for both excellent quality and low-bandwidth results. Motion estimation step (ME), for...
This paper has presented a novel dual-band bandpass filter with two sets of resonators based on stepped-impedance, which can achieve size reduction. Two sets of resonators are employed in the filter, one resonate at the 60 GHz and the other at the 77 GHz. The dual-band filter can be realized flexible passband and bandwidth selections by utilizing impedance varying and source-load coupling. The fractional...
This paper explores a common-emitter buffer-based frequency multiplier which can be applied to the voltage-controlled oscillator (VCO) to boost the output frequency of the VCO. A VCO with a frequency quadrupler is designed and verify with this technique in 130nm SiGe BiCMOS technology. The post-layout simulation shows this VCO can be tuned from 287 to 294.5GHz. The output power into a 50 Ω load is...
This paper presents a novel methodology for fault diagnosis in gas turbine engines based on the concept of dynamic neural networks. The neural network structure belongs to the class of locally recurrent globally feed-forward networks. The architecture of the network is similar to the feed-forward multi-layer perceptron with the difference that the processing units include dynamic characteristics....
This paper investigates a method for controlling a class of nonlinear systems over a communication network with the consideration of network-induced and sampling time delays, packet losses, and quantization errors. In order to represent continuous-time nonlinear systems, Takagi-Sugeno (T-S) fuzzy model is employed, based on which a networked control system (NCS) is designed so that all the states...
Operation of a MOS RLC-oscillator is considered, and it is shown that it can be described by the van der Pol model. The transformation of time scale to the oscillator intrinsic time allows one to use the previously obtained results for harmonic content of the van der Pol model. One can calculate the total harmonic distortions and use it to design an oscillator with required level of them. The correction...
In this paper, we investigate and compare the effectiveness of different charge sharing techniques for reduction of charge sharing and collection among adjacent nodes in 65-nm technology NFET transistors. We use Synopsys 2-D TCAD mixed-mode simulations to measure collected charge at a node adjacent to a device struck by a heavy-ion particle for cases of using Shallow Trench Isolation (STI), Deep Trench...
This paper presents a symmetrical readout circuit for capacitive sensors. Based on charge transfer principle, it is insensitive to stray capacitors. Introducing a reference branch, this symmetrical readout circuit can enlarge its linear range, reduce amplifier offsets and reject common-mode noise and even-order distortions. Chopper stabilization technique is used to reduce the negative effects of...
As telecommunications networks transition from TDM to IP packet technologies, network timing and synchronization will need to evolve to support the new IP-based infrastructure. Work is already underway within the standards bodies and working groups to develop equivalent mechanisms to support packet-based synchronization technologies. These may be at the Layer 1 level with physical layer synchronization,...
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