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A rugged method for distance estimation based on an OFDM signal combined with the Zadoff-Chu sequences is introduced. A software algorithm extracts a coarse distance in time domain exploiting the Zadoff-Chu properties. The distance, then, is fine adjusted evaluating the time offset from the subcarriers phase. Several tests were performed in laboratory considering a very harsh indoor environment and...
This work exploits the well-known gm over ID methodology to develop a novel approach to optimize the design of regulated cascode amplifiers (RgC). The proposed design framework starts extracting a set of lookup tables describing the circuit's figures of merit as a function of the gm over ID ratio. Due to the feedback topology of the circuit, the performances, in terms of bandwidth, gain, and DC power...
This work presents the design and implementation of a low-complexity beam steering polar transceiver based on a revised DDS-PLL phase shifter architecture. The proposed modulator-less topology targets narrowband communications for enhanced Internet-of-Things systems, and has been prototyped using an FPGA evaluation board and a custom PCB with four PLLs centered at 2.453-GHz. Measured system performance...
This paper presents a new framework for the design optimization of a CMOS down-conversion mixer based on a conventional double balanced Gilbert cell. The framework exploits the gm/ID methodology to find the transistors' dimensions that optimize the tradeoff between conversion gain, noise figure, third-order intercept and power DC consumption of the mixer. The mixer has been designed using a 0.13 μm...
A novel method for distance estimation is introduced, based on an OFDM signal combined with the Zadoff-Chu Sequences. By exploiting the properties of these sequences it is possible to evaluate the distance between a transmitter and a receiver with a very good precision and accuracy. The technique effectiveness is demonstrated in a real operating environment by measuring the distance between two active...
The paper presents a systematic methodology for designing a CMOS down-conversion mixer based on a conventional double balanced Gilbert cell. The design flow exploits the gm/ID methodology in order to optimize the size of the transistors that allow achieving the best tradeoff between conversion gain, noise figure, third-order intercept and power DC consumption of the entire system. The mixer was designed...
The paper presents a wearable wireless system and a proprietary algorithm along with a preliminary study on the time gait variability analysis as a tool for early diagnosis. The system is non-invasive and it is composed by a set of Inertial Measurements Units (IMUs) positioned on the patient leg. Each unit in the set bases its operations on Bluetooth Low Energy (BLE) standard. Experimental results...
The paper introduces a novel method for distance estimation based on an OFDM signal combined with the Zadoff-Chu sequences. By exploiting the properties of these sequences, it is possible to evaluate the distance between two active nodes with a very good precision and accuracy. The technique effectiveness is demonstrated by measuring the distance between a single transmitter and a synchronized receiver...
This paper introduces an architecture capable of generating four mutually phase shifted radio frequency signals for beam steering of active phased array antennas (APAAs) to be eventually integrated into a single Application Specific Integrated Circuit (ASIC). Targeting space and weight constrained applications, the proposed architecture features an 8051 IP-core and four custom DDS-PLL phase shifters...
This paper presents the optimized design of a conventional four-stage distributed amplifier for Ultra-Wide Band applications (UWB). The design flow exploits the gm/ID methodology in order to optimize the size of the transistors to achieve the best tradeoff between gain, input/output matching, noise figure and power DC consumption. The circuit was designed using a 0.13 μm process from IHP Microelectronics,...
This paper presents a framework for the systematic design of inductor-less regulated cascode (RGC) stages. Targeting high-speed fiber optic data receiver front-ends, the technique reported combines the symbolic solution of the small-signal model of the RGC and the use of gm/ID based lookup tables to efficiently explore and optimize the resulting design space. A practical design is discussed and implemented...
In this paper we exploit the gm over ID methodology to optimize the design of a four stage conventional Distributed Amplifier (DA) for an Ultra-Wide Band positioning system. The W/L ratio and the DC-biasing of the amplifier's transistors are determined according to the gm over ID methodology by using a series of lookup tables generated starting from the model of the devices. The DA was designed using...
This paper introduces the design and implementation of a high performance, reconfigurable four channel beam steering unit (BSU) for active phased-array antennas based on FPGA synthesized delay-lines and PLLs. The unit allows a per channel programmable time delay equivalent to a phase shift tuning step of about 1.4°. A prototype has been implemented to validate the viability of the proposed approach...
This paper introduces the design and implementation of a new programmable phase control unit (PCU) topology for active phased array antennas. The array is based on a hybrid direct digital synthesizer (DDS) phase-lock-loop (PLL) approach. The PCU generates up to 1024 phase shift values programmable in the form of phase-offset words by either a microcontroller or a DSP. As a result a 360° phase shifting...
The paper introduces a linearization technique based on a modified complex gain predistorter. The look-up table (LUT) digital adaptive predistortion (PD) approaches are effective for power amplifier (PA) linearization for reducing the PA power back-off and increasing the efficiency. Unlike other LUT predistorter based on uniform spacing of the LUT entries, the paper proposes a robust and behavioral...
The paper describes a Track and Hold Amplifier (THA) suitable for RF sampling and Software Defined Radio receivers where high speed and high resolution are required. The reported THA is based on two main techniques: one for minimizing the differential droop rate and one for improving the HD3 in track mode. Measurements results show that the adopted solutions are both effective. In the desired input...
A novel input buffer for very high speed and high resolution track-andhold amplifiers has been developed in BiCMOS technology. The configuration retains the benefits of a cascode configuration in terms of distortion and adaptability to various advanced switched-emitter (source)- follower based architectures while maintaining supply requirements similar to a conventional degenerated common emitter...
The paper describes a SIMULINK® model for the complete time-domain behavioral simulation of A to D converter. In general standard CAD models are lacking in utility, since they do not model all the sources of errors. In this paper, the main parameters which affect the operations of this device are investigated and the relative non-idealities effects are modeled. The black-box description can be used...
The paper describes a new digitally programmable multi-band precise quadrature generator. The proposed approach leads to high-phase resolution joint to uniform performances in all the sub-bands of synthesis. It is easily scalable in frequency and suitable to implement any calibration technique to compensate the typical phase imbalance generated in the front end. The theory governing the quadrature...
The paper presents a wideband fully differential operational amplifier in 0.35μm SiGe technology. The circuit provides a gain of 94dB and a 1.6GHz unity gain bandwidth drawing 25 mA from 3.3V supply voltage. The circuit employs a novel class AB output stage and it was used to generate wideband low impedance voltage references for a high speed A/D converter.
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