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Since its acceptance as the adopted authenticated encryption algorithm, AES-GCM has been utilized in various security-constrained applications. This paper describes the benefits of adding key-synthesized property to AES-GCM using FPGAs. Presented architectures can be used for applications which require encryption and authentication with slow changing keys like Virtual Private Networks (VPNs). Our...
Particle filters (PFs) are computationally intensive, which prevents them from being widely used in some real-time applications with high throughput requirements. A parallel implementation is a feasible approach to enable using PFs in these applications. However, effective resampling algorithms such as the Systematic Resampling (SR) algorithm are sequential in nature. In this paper, we propose a new...
In this paper we apply predictor-based system identification technique to unstable system to identify system dynamics. Due to instability, we need to avoid diverging output by designing controller which can keep the system poles inside unit circle in discrete time domain. This technique is applied to identify highly oscillatory wind turbine systems. In both cases, the I/O data collected by forming...
In this paper an algorithm is proposed to plan the path taken by a robot in order to reach a specific coordinate. This algorithm is proposed to be used in a robot with a synchronous propulsion architecture, because this architecture improves robot odometry and is not common in navigation tasks, mapping and localization. Furthermore, this algorithm determines the shortest path with respect to the resolution...
Foggy image enhancement is an important branch of digital image processing, which significantly benefits traffic and outdoor visual systems. To overcome the shortcomings of the existing foggy image enhancement algorithms, we have developed a method that combines Principal Component Analysis (PCA), Multi-Scale Retinex (MSR) and Global Histogram Equalization (GHE). Initially, a PCA transform is applied...
This paper describes the design of a custom robotic system that will be used for clinical evaluation of upper-limb motor performance. The system consists of a mechatronic component that is central to capturing of motor inputs, and a software component that constitutes various user interface applications. The focus of this paper is to elaborate the design of the mechatronic component and how it integrates...
In this work, we present a novel structure of Graphene NanoRibbon Field-Effect Transistor (GNR FET) to reduce short channel effects. In this structure, two side metal gates with lower work-function than the main gate are used in a conventional double-gate (DG) GNR FET topology to provide virtual extensions to source/drain regions while these are biased constant, independent of the main gate. The proposed...
A simplified expression for the current-excited step response of the Cole impedance model which significantly reduces the numerical complexity required to extract the impedance parameters using a nonlinear least squares fitting is presented. MATLAB simulations show reductions in extraction times up to 47.5%, without reducing extraction accuracy and are verified experimentally on an ideal Cole-model...
This paper describes an FM-UWB transceiver system which employs M-PSK modulated subcarriers for high throughput data transmission. Compared to conventional 2-FSK FM-UWB transceivers, the proposed M-PSK FM-UWB transceiver can increase data rate with minimal increment of RF front-end complexity. A regenerative FM demodulator followed by a low-frequency M-PSK demodulator enables low-power low-cost receiver...
In this paper, we investigate the channel estimation algorithm for medium-voltage, long haul power line communi-cation (PLC) system in the IEEE 1901 standard. To improve the overall performance, we employ a dual Gaussian interpolation method working on the amplitude and phase domain simultane-ously, a major difference from the conventional schemes using the real and imaginary part. Meanwhile, to mitigate...
Reliability is a crucial factor in modern processors, which are designed in deep sub-micron (DSM) technologies and perform numerous tasks at high speed in less time. Modern DSM technologies are even more vulnerable to soft errors, which can propagate in pipeline processors and may lead to malfunctioning. Contemporary soft error mitigation techniques introduce redundancy in intermediate registers alone...
In this work, a steady-state analysis and a fast optimisation approach based upon it are implemented to analyse the class-E PA. With this approach, the component values and performance of class-E PA with RFC and parallel-circuit load (PCL) are analysed and compared. One fast search approach is developed for various constrained/unconstrained optimisations. The analysis, fast optimisation approach and...
A systematic design methodology utilizing piecewise curvature correction technique for the purpose of improving the temperature coefficient of bandgap references (BGRs) is presented in this paper. It is shown that the temperature dependency of the drain current of a MOSFET transistor depends on the transistor's operating region. Using this property, a multi-piecewise compensation technique over wide...
This paper presents a z-domain model for voltage-doubler charge pumps that considers the variations of both input voltage and load current. We show how the model can be used to design an efficient control system for a typical charge pump. The application of the model is demonstrated through circuit simulations of a regulated charge pump, designed to keep area and energy consumption low.
We present a large-scale Field Programmable Analog Array (FPAA) that enables floating-gate adaptive circuits using Floating-Gate(FG) based switch technology. We present a novel architecture technology that enables switch routing with FG elements for signals resulting from high voltage adapting FG elements. We present careful analysis and characterization of the FG structure, including programming...
In this paper, a new 96 × 96 30 µm pitch mixed-signal readout integrated circuit (ROIC) with a pixel-level tunable bias control is demonstrated. The new ROIC is capable of providing a large bias voltage in both polarities on each individual pixel, independently. These enhanced functionalities are achieved by modifying a capacitive transimpedance amplifier (CTIA) CMOS ROIC architecture. In addition...
An architecture for a combinational floating point multiplier and squarer is described for the purpose of producing a low power floating point square with small area requirements. The floating-point multiplier and squarer architecture are compared to demonstrate the power advantage of the squarer. The multiplier and squarer are combined into one circuit in order to take advantage of the squarer power...
Proposed innovation gives a faster, lower depth, lower power and lower area solution for addition. The paper describes two novel static gates developed for 4-bit Majority Carry Generate (MCG) and Majority Carry Propagate (MCP) operation in a single gate depth. Derivation of a novel 72-bit CL2A within 6 gate-depth, using MCG, MCP and a novel sparse5 (5×2n) algorithm with a variable sparse is described...
A novel compressive sampling scheme suitable for highly scalable hardware implementations is presented. The prototype design is implemented in a 0.18µm standard CMOS technology and utilizes compressed acquisition to boost the overall power efficiency. Specialized pixels, convenient for Comparator-Based Switched Capacitor readout are developed for this purpose. A custom measurement matrix generation...
Recent advances in signal processing hardware has made possible the implementation of sophisticated algorithms. The Complex Block Conjugate Least Mean Square algorithm with Individual adaptation (CBCI-LMS) has recently been proposed and applied in adaptive filtering applications. This technique involves matrix inversion, which is computationally intensive. To improve the feasibility of the algorithm...
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