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An increasing number of applications rely on embedded systems for a correct behavior or user interaction. Many of these systems are today considered critical (for safety, security ... or just for competitiveness), but cannot be expensive and often need flexibility. SRAM-based FPGAs are good candidates to implement such systems but their main disadvantage is their relatively high probability of application...
A parallel algorithm for a full-digital phase-locked loop for high-throughput adaptive carrier and timing recovery systems has been developed. The proposed algorithm separately estimates an initial phase and a period fluctuation for a sampled signal, whereas they are simultaneously estimated by conventional algorithms. The new algorithm increases the pull-in frequency range by 1.6 times and reduces...
The main objective of this educational paper is to provide an updated survey of ASIC and FPGA technologies' convergence in reconfigurable and embedded systems. Through the analysis of design methodologies and strategies facing multi-core and power consumption challenges we will follow that evolution approaching ASIC and FPGA architectures on the embedded systems arena.
A new technique, Amplifier and Comparator Based Switched Capacitor (ACBSC) for low voltage switched cap circuits, is presented. ACBSC combines the recently introduced CBSC (comparator based switched capacitor circuit) with an amplifier. The current sources in ACBSC experience less output voltage swing compared to the ones in CBSC. We apply ACBSC to the design of a 3rd-order sigma delta modulator in...
A Frequency-to-voltage converter (FVC) for use in a system for feedback linearization of VCOs is presented. The VCO linearization is intended for use in an ADC application where high resolution, low power consumption, and low voltage operation is required. These requirements places stringent demands on the performance of the FVC. The proposed implementation of the FVC is a good fit for digital CMOS...
A novel built-in self calibration technique for single-loop continuous-time sigma-delta modulators is proposed. Using out-of-band test signal injection and digital cancellation, this technique provides an area efficient, highly digital calibration structure to counteract gain variations in the loop filter. The calibration methodology and mathematical analysis are presented using a 2nd order multibit...
This paper outlines a solution technique developed for frequency-domain analysis and synthesis of linear time-varying (LTV) systems. By an application of two-sided Laplace transform and two-dimensional Laplace Transform (2DLT), in general, the frequency-domain techniques are developed, which facilitate the analysis or synthesis of variable and adaptive systems. The significant advantage of the frequency...
A novel technique for the remote reading of chipless capacitive sensor Tags and one of its possible applications is presented. For this purpose, a frequency agile reader has been developed using Software Defined Radio (SDR) architectures, capable of scanning with high precision a frequency range given by an external user and extracting the resonant frequency of a Tag. The capacitive sensor Tag has...
In this paper, a procedure for characterization and modeling of LC-tanks is proposed to enhance simulation accuracy in design of monolithic Voltage Controlled Oscillators (VCO). This efficient procedure is easy to implement combining robust design of G-S-G (Ground-Signal-Ground) test structures and accurate on-wafer characterizations, and it is in particular suitable for modeling of high frequency...
The brushless DC (BLDC) motors have become the common choice in low power, high speed, high accuracy applications and this imposed the need for efficient and low cost motor control drives. In this paper, a design method for a digital controller implemented in a low cost field programmable gate array (FPGA) is presented. The design is done by schematic capture and Simulink block diagram capture. The...
The main objective of this paper is to enhance the university's monitoring system taking into account factors such as reliability, time saving, and easy control. The proposed system consists of a mobile RFID solution in a logical context. The system prototype and its small scale application was a complete success. However, the more practical phase will not be immediately ready because a large setup...
This paper presents an architecture of an IR-UWB MB-OOK non-coherent transceiver. Channel measurements performed for both LOS and NLOS short-range communications in real indoor environment based on this realized prototype are provided. A comparison between the use of directional and omnidirectional antennas at both emission and reception is presented. Then, an estimation of the data rate of the communicating...
An analytical model of the photoresponse of p-n junctions under a point source illumination is presented. The model measures the response of different regions of the pixel in terms of current. Both p-n+ and p-Nwell junction photodiodes were fabricated in a standard UMC 90nm technology and tested. Model and experimental data reveal a similar behaviour.
The design, manufacture and deployment of embedded systems become increasingly complex and multidisciplinary process. Before the steps of manufacturing and deployment, a simulation and validation phase is necessary. Given the increasing complexity of systems such as telecommunications systems, control systems and others, a specific simulation and validation process must take place. This simulation...
This paper presents the hardware implementation and verification of an FPGA-based DMX512 decoder using VHDL as a Hardware Description Language. The implementation is proposed to provide a single chip solution to decode the DMX512 serial data generated from a control desk, whilst providing control data and processing mechanisms on the same chip. In particular, such an FPGA solution would be superior...
This paper describes an original stream implementation of serially composed morphological filters using approximated flat polygons. It strictly respects a sequential data access. Results are obtained with minimal latency while operating within minimal memory space; even for very large neighborhoods. This is interesting for serially composed advanced filters, such as Alternating Sequential Filters...
Estimating a system's complexity is essential before making a decision about the architecture to be built or not. Especially for mobile User Equipments (UE) complexity is a big issue. Reduced complexity, mainly meaning reduced number of additions and multiplications in a system, is highly desired also to minimize power consumption. In order to be able to compare different systems and architectures,...
Digital Signal Processing (DSP) applications are widely used from wireless communications to automotive. Their ever growing complexity and throughput still require significant parts to be implemented as dedicated hardware accelerators. A High-Level Synthesis (HLS) flow to automatically generate hardware accelerators for DSP applications is proposed in this paper. By considering bit-width information...
Leakage power (active and standby) is becoming increasingly dominant part of total power consumption in nano-scaled CMOS circuits. Present day commercial libraries provide multiple vt class cells to optimize active leakage power and circuit timing in functional/active mode, while techniques such as power gating have specifically addressed standby leakage reduction. However, the total leakage power...
Log-domain filters with maximized dynamic range are presented in this paper. This is achieved by employing enhanced lossless and lossy integrator blocks, where independent scaling of their input weight factors is performed. It should be mentioned at this point that the maximization of the dynamic range is achieved without losing the benefit of log-domain filters for electronically adjusting their...
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