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Timing problems in high-speed serial communications are mitigated with phase-interpolator (PI) circuitry. Linearity testing of PI has been challenging, even though PI is widely used in modern high speed I/O architectures. Previous research has focused on implementing additional built-in circuits to measure PI linearity. In this paper, we present a cost effective PI linearity measurement technique...
This paper describes a RMS value measurement technique for random jitter. A jittery clock signal is combined with a reference clock signal using an OR operation and an AND operation in sequence, and the pulse width outputs modulated by the amount of the random jitter are used to charge or discharge a capacitor. The voltage at the capacitor, in turn, modulates the frequency of VCO having a current-starved...
This paper presents an efficient pseudorandom (PR) test method to characterize the performance of nonlinear analog and mixed-signal (AMS) circuits including those embedded in SoC devices. Previous applications of the PR test method to BIST have been limited to digital and linear analog circuits. In this paper, we extend the application of PR test to nonlinear AMS circuits. In doing so, we reduce the...
A novel technique for implementing very high speed FFTs based on unrolled CORDIC structures is proposed in this paper. There has been a lot of research in the area of FFT algorithm implementation; most of the research is focused on reduction of the computational complexity by selection and efficient decomposition of the FFT algorithm. However there has not been much research on using the CORDIC structures...
This paper presents a SNR-aware error detection technique for a low-power wavelet lifting transform architecture in JPEG 2000. Power reduction is done by over-scaling the supply voltage (voltage-over-scaling (VOS)). A low-cost SNR-aware detection logic is integrated into the discrete wavelet lifting transform architecture, to check if the image quality degradation caused by the resulting timing errors...
Mixed signal circuits typically require more complex specification based testing as compared to digital circuits, which can be completely tested with structural or simple functional tests. Due to the analog nature of some of the internal nodes and external signals in mixed signal circuits, qualitative functional tests may be required to assure circuit performance at all operating points. Mixed signal...
A fault coverage analysis has become an important tool to evaluate the testability of developing circuits and to come up with an effective test plan. However, the fault coverage analysis of analog circuits has not gained much attention due to the long fault simulation time and the absence of widely accepted fault models. This paper presents an efficient framework for the analog fault coverage analysis...
Discrete Wavelet transform is a powerful mathematics technique which is being adopted in different applications including physics, image processing, biomedical signal processing, and communication. Due to its pipelined structure and multirate processing requirements, a single numerical error in one stage can easily affect multiple outputs in final result. In this paper, we propose a weighted checksum...
Skew calibration and compensation are critical ATE features for reliable functional test, particularly for applications such as memory chips. This paper presents a new time-to-digital converter (TDC) design for off-chip skew calibration from time domain reflectometry (TDR) measurements. It consists of coarse and fine parts which enable the circuit to detect a large skew range with high resolution...
Identifying the set of real critical paths of a circuit is an important step in delay testing. Since path delays are vector dependent, the set of critical paths selected depends on the vectors assumed when estimating the path delays. To find the real critical paths, it is important to consider the effect of dynamic (vector dependent) delay effects such as coupling noise, supply noise etc. during path...
As the supply voltage shrinks with technology scaling, the slightest drop in the voltage level has a significant impact on chip functionality. It is, therefore, important to accurately measure supply voltage noise to evaluate the actual IR drop on-chip and to feed the results to a power management unit, which can scale the voltage and perform on-chip compensation based on the IR drop. In this paper,...
This paper presents a new path selection algorithm for delay fault testing in a statistical timing framework. Existing algorithms which consider correlation between paths use an iterative process for each path or defect and require a Monte Carlo simulation for each iteration to calculate the conditional fault probability. The proposed algorithm does not require the iteration process and selects a...
The cost of testing mixed signal circuitry with conventional analog-stimulus is significantly higher than digital circuitry due to higher cost automatic test equipment (ATE) required for generation of analog stimulus. Multiple variants of low cost testers have been developed for digital testing which rely on relaxed timing, power or tester channel requirements to lower hardware cost. Systems containing...
This paper develops a technique, using a built-in detector, for measuring the specifications of RF subsystems and fine-tuning them with a feedback control algorithm. At the same time, optimum power consumption points can be chosen from different biasing schemes. The detector has small area overhead with low frequency output. The sampled output waveform is analyzed using an FFT. The low frequency measurements...
Traditionally, peak power consumption has been estimated at the module-level and there has been no attempt to check the functional validity of the gate-level estimate through instruction execution. This leads to the over design of the processor components that deliver current to the modules. In this work, we present a methodology to estimate the peak dynamic power at the module-level which is functionally...
For timing analysis, each flip-flop and latch in a standard library is characterized for two constraints: setup time and hold time constraints. These constraints need to be characterized for their sensitivities to the variation parameters in order to perform statistical timing analysis. Several approaches have been proposed to perform statistical characterization of delays. However, the predominant...
This paper shows that a timing graph has a hierarchy of specially defined subgraphs, based on which we present a technique that captures topological correlation in arbitrary block-based statistical static timing analysis (SSTA). We interpret a timing graph as an algebraic expression made up of addition and maximum operators. We define the division operation on the expression and propose algorithms...
We present dedicated rewriting, a novel technique to automatically prove the correctness of low power transformations in hardware systems described at the Register Transfer Level (RTL). We guarantee the correctness of any low power transformation by providing a functional equivalence proof of the hardware design before and after the transformation. We characterize low power transformations as rules,...
With the adoption of statistical timing across industry, there is a need to characterize all gates/cells in a digital library for delay variation (referred to as statistical characterization). Statistical characterization needs to be performed efficiently with acceptable accuracy as a function of several process and environmental parameter variations. In this paper, we propose an approach to consider...
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