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As we move deeper in the nanotechnology era, computer architecture is solicited to manipulate tremendous numbers of devices per chip with high defect densities. These trends provide new computing opportunities but efficiently exploiting them will require a shift towards novel, highly parallel architectures. Fault tolerant mechanisms will have to be integrated to the design to deal with the low yield...
This paper presents the results of alpha single event upsets tests of an embedded 8051 microprocessor. Cross sections for the different memory resources (i.e., internal registers, code RAM, and user memory) are reported as well as the error rate for different codes implemented as test benchmarks. Test results are then discussed to find the contribution of each available resource to the overall device...
This paper presents an innovative method that allows the use of dynamic partial reconfiguration combined with triple modular redundancy (TMR) in SRAM-based FPGAs fault-tolerant designs. The method combines large grain TMR with special voters capable of signalizing the faulty module and check point states that allow the sequential synchronization of the recovered module with the Xilinx TMR (XTMR) approach...
Aggressive voltage scaling needed for low power in each new process generation causes large deviations in the threshold voltage of minimally sized devices of the 6T SRAM cell. Gate oxide scaling can cause large transient gate leakage (a trap in the gate oxide), which is known as the erratic bits phenomena. Register file protection is necessary to prevent errors from quickly spreading to different...
In this work we analyze the effects of radiation-induced transient pulses on 6T SRAM cells operating in read mode. The critical charge of a memory cell during read mode is lower than in hold mode. For 1 to 0 upsets, this reduction reaches a factor x 1.5 for events produced by alpha particles; this factor is even higher for longer induced current pulses. The impact of events propagated through the...
Radiation-hardened-by-design (RHBD) SRAM-based FPGAs will play a crucial role in providing new generations of satellites with reliable in-flight reconfiguration ability, which is mandatory to enable the successful use of configurable computing in space. RHBD SRAM-based FPGAs sensitiveness against ionizing radiation is normally evaluated resorting to radiation testing, which provides the device cross-section...
We present an low-cost enhancement to a standard MISR design for safety and security purposes in automotive applications. Depending on the application, the MISR is enhanced by either a linear or a nonlinear code generator presented in this paper. Linear code generator reduces the probability of error masking for a BIST-related signature generation while nonlinear code generator is used for security-related...
We propose an approach to optimize the number of checkpoints to be inserted along with an application code. The approach is based on a profiling process that analyzes the application code control-flow graph to find the best trade-off between the minimum number of checkpoints to be inserted in the code for a given fault detection coverage, with minimum impact in terms of power increase. The checkpoints...
Observability is mandatory for debugging purposes in all microelectronic systems. Mixed signal cores, in particular, require high observability in order to allow post production debug and to drive the design enhancements towards the real non-ideal behaviour monitored in individual modules. Controllability is also a major advantage in the design-for-debug process. This work presents a low cost controllability...
Dependable architectures play an important role in many areas that impact our lives. Dependability is achieved by using a set of analysis and design techniques that increases the complexity and consequently the cost of systems. In this paper, to meet low cost requirement of IP cores, we propose a simple dependable stack processor architecture using a re-execution model of instructions in the case...
The presentation concerns a practical approach for dealing with difficulties associated to real time testing in a natural environment of microelectronic devices. This activity has several redeeming characteristics that make it very interesting for reliability engineers that are concerned with the Single Event Effects (SEEs) affecting the functioning of their devices in a natural working environment...
Testing of cryptographic chips or components has one extra dimension: physical security. The chip designers should improve the design if it leaks too much information through side-channels, such as timing, power consumption, electric-magnetic radiation, and so on. This requires an evaluation of the security level of the chip under different side-channel attacks before it is manufactured. This paper...
The goal of this work is to confront SER predictions done with MUSCA SEP3 to measures performed at high altitude (in commercial planes) by means a generic and flexible experimental testboard developed by TIMA. In this case the testboard was a memory architecture of 1 Gigabit made from SRAMs issued from two successive generations, 130 nm and 90 nm, respectively named models 1 and 2 in the following.
Resistive opens in vias and interconnection lines have become an issue in modern nanometer technologies. These defects may produce small delays which are difficult to detect and may pose a reliability problem. In this paper, a statistical timing analysis framework is used to analyze the detectability of small delays due to resistive opens considering process variations. A statistical methodology to...
As technology scales, designing a massively parallel multi-cores system atop less reliable hardware architecture poses great challenges for researchers and designers. In this environment, ignoring variation effects when scheduling applications or when managing power with Dynamic Voltage and Frequency Scaling (DVFS) is suboptimal. We present a variation-aware multi-level scheduling and power management...
The amount of physical variation among electronic components on a die is increasing rapidly. There is a need for a better understanding of variations in transient fault susceptibility, and for methods of on-line adaptation to such variations. We address three key research questions in this area. First, we investigate accelerated characterization of individual latch susceptibilities. We find that on...
The paper deals with designing fault tolerant finite state machines (FSMs) by nanoelectronic programmable logic arrays (PLAs). Two main critical parameters of the fault tolerant nano-PLAs, the area and the number of crosspoint devices, are considered as optimization criteria for the synthesis. The paper introduces a method for synthesizing fault tolerant nano-PLA based FSMs. The method is based on...
This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bit and multiple-bit transient faults. The Power-Delay Product (PDP) and area overheads of this technique are decreased at least 82% and 71%, respectively,...
Semiconductor technology evolution brings along higher soft error rates and long duration transients, which require new low cost system level approaches for error detection and mitigation. Known software based error detection techniques imply a high overhead in terms of memory usage and execution times. In this work, the use of software invariants as a means to detect transient errors affecting a...
Complex electronic systems for safety or mission-critical applications (automotive, space) must operate for many years in harsh environments. Reliability issues are worsening with device scaling down, while performance and quality requirements are increasing. One of the key reliability issues is to monitor long-term performance degradation due to aging in such harsh environments. For safe operation,...
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