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The following topics on quality electronic designs are dealt with: aging aware design; robust circuits; electronic design library and modelling; circuits noise; process variations; embedded systems; system level modeling and design; system and interface validation; digital design; IC packaging; memory design solutions; polyanalysis and delivery system; timing analysis and floor planning;low voltage...
On-chip circuit aging sources, like negative bias temperature instability (NBTI), hot-carrier injection (HCI), electromigration, and oxide breakdown, are reducing expected chip lifetimes. Being able to track the actual aging process is one way to avoid unnecessarily large design margins. This work proposes a sensing scheme that uses sets of reliability sensors capable of accurately tracking NBTI PMOS...
A unified FinFET reliability model including high K stack dynamic threshold (HKSDT), hot carrier injection (HCI), and negative bias temperature instability (NBTI) has been developed and verified by experimental data. The FinFET-based circuit performances are simulated and compared under these reliability issues by HSPICE simulator after the inclusion of the presented model.
This work establishes an analytical model framework to account for the NBTI aging effect on statistical circuit delay distribution. In this paper, we explain how circuit NBTI mitigation techniques can account for this extra variability and further present the impact of statistical PMOS NBTI DC-lifetime variability on the product delay spread.
As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concerns for circuit designers. Consequently, we have seen a lot of research efforts on NBTI analysis and mitigation techniques. On the other hand, reducing leakage power remains to be one of the major design goals. Both NBTI-induced circuit degradation and standby leakage power...
We describe here, the design and use of a unique test chip on power and variability (TPV) to measure and report for the first time, the magnitude of leakage and dynamic power dissipation and its variation. This test chip, fabricated in a state-of-the-art 45 nm process node technology, addresses the important issues of variability in power and delay and quantifies them as a function of voltage and...
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