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As the complexity of integrated circuit design increases and production schedules become shorter, the dependency on post-silicon validation for capturing design errors that escape from pre-silicon verification also increases. A major challenge in post-silicon validation is the limited observability of internal states caused by the limited storage capacity available for post-silicon validation. Recent...
In order to gain market share in today's competitive high-tech industry, fast time-to-market (TTM) is one of the key factors for the success of a product. Since pre-silicon verification cannot be applied exhaustively as the size and complexity of the integrated circuit design increases, post-silicon validation becomes crucial to capture bugs and design errors that escape from the pre-silicon verification...
Skew calibration and compensation are critical ATE features for reliable functional test, particularly for applications such as memory chips since most mainstream memories use a source-synchronous interface. This paper presents a new Skew Measurement and Compensation Module (SMCM) design for off-chip skew calibration from Time Domain Reflectometry (TDR) measurements. It consists of coarse and fine...
This paper presents an efficient test framework to extend a use of low-cost ATE (Automatic Test Equipment) to at-speed test of high-speed DUT (Device Under Test). To bridge the speed gap between the ATE and the DUT, an off-chip test interface circuit, called Built-off Test Interface (BOTI), has been developed. Unlike the previous methods which use on-chip or off-chip self-test circuits, in our method,...
Skew calibration and compensation are critical ATE features for reliable functional test, particularly for applications such as memory chips. This paper presents a new time-to-digital converter (TDC) design for off-chip skew calibration from time domain reflectometry (TDR) measurements. It consists of coarse and fine parts which enable the circuit to detect a large skew range with high resolution...
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