Search results for: Sajad A. Loan

Items from 1 to 20 out of 32 results

article

High performance accelerators for deep neural networks: A review

Mohd Saqib Akhoon, Shahrel A. Suandi, Abdullah Alshahrani, Abdul‐Malik H. Y. Saad, more

The availability of huge structured and unstructured data, advanced highly dense memory and high performance computing machines have provided a strong push for the development in artificial intelligence (AI) and machine learning (ML) domains. AI and machine learning has rekindled the hope of efficiently solving complex problems which was not possible in the recent past. The generation and availability...

article

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

Ashita, Sajad A. Loan, Hend I. Alkhammash, Mohammad Rafat

International Journal of Numerical Modelling: Electronic Networks, Devices... > 34 > 5 > n/a - n/a

In this work, we propose and investigate a new pocket‐based Si_0.55Ge_0.45/Si gate normal tunnel FET design employing a gate over source with a single lateral pocket (GSLP) with and without a heterogeneous dielectric (HD) gate oxide. Miller capacitance is significantly reduced with the GSLP design, which is further improved by the HD gate oxide leading to full overshoot/undershoot suppression capability...

article

CNTFET‐based active grounded inductor using positive and negative current conveyors and applications

Seema Jogad, Hend I. Alkhammash, Neelofer Afzal, Sajad A. Loan

International Journal of Numerical Modelling: Electronic Networks, Devices... > 34 > 5 > n/a - n/a

In this work, we design and simulate novel 32 nm carbon nanotube field effect transistor (CNTFET) as well as complementary metal oxide semiconductor (CMOS)‐based negative class AB second generation current conveyors (CC) (CNTFET‐CCII and CMOS‐CCII−). The comparative analyses of various performance measuring parameters of both these CCII's have been performed. A significant improvement in current and...

article

Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

Mohd Haris, Sajad A. Loan, Mainuddin

International Journal of Numerical Modelling: Electronic Networks, Devices... > 34 > 2 > n/a - n/a

In this work, we present the design and simulation of a novel structure of In_0.53Ga_0.43As/InP based hetero junction tunnel field effect transistor (HTFET). The proposed HTFET employs two gates: the conventional main gate and a pseudo split gate (PSG) at the drain side. The PSG is placed at the top of the drain region with the same equivalent oxide thickness (EOT) and work function as that of the main...

article

CNTFET based class AB current conveyor II: Design, analysis and waveform generator applications

Seema Jogad, Sajad A. Loan, Neelofer Afzal, Abdullah G. Alharbi

International Journal of Numerical Modelling: Electronic Networks, Devices... > 34 > 1 > n/a - n/a

In this work, we design and simulate a new class AB second generation current conveyor (CCII) employing 32 nm technology node carbon nanotube field effect transistors (CNTFET). The performance of the proposed CNTFET based class AB CCII (CNTFET‐CCII) has been optimized by altering the number of carbon nanotubes (CNTs) (N), CNT pitch (S), and CNT diameter (D_CNT). The proposed CCII has been compared...

article

Electrostatically doped drain engineered DG‐TFET: Proposal and analysis

Mohd Rizwan Uddin Shaikh, Sajad A. Loan, Abdullah Alshahrani

International Journal of Numerical Modelling: Electronic Networks, Devices... > 33 > 6 > n/a - n/a

In this paper, a drain‐engineered double‐gate Tunnel‐FET (DE‐DG‐TFET) to enhance the electrical characteristics and analog parameters of a conventional DG‐TFET is proposed and examined through calibrated TCAD simulations. Unlike DG‐TFET, a constant n‐type doping, N_cd, (5 × 10¹⁷ cm⁻³ − 2 × 10¹⁸ cm⁻³), in the channel/drain regions of DE‐DG‐TFET is used, resulting in a p⁺‐n‐n structure instead of conventional...

article

A normally OFF GaN CAVET and its thermal and trap analysis

Sumit Verma, M. Saqib Akhoon, Sajad A. Loan, Mana Al Reshan

Journal of Computational Electronics > 2019 > 18 > 3 > 941-950

We propose and investigate an enhancement-mode (normally OFF) current-aperture vertical electron transistor (CAVET) with a novel structure. The novelty lies in the achievement of the desired normally OFF/enhancement-mode operation through polarization engineering by employing a hybrid current-blocking layer (HCBL) made of an isolation material and aluminum nitride (AlN). The AlN introduces a conduction...

article

Electrostatically Doped DSL Schottky Barrier MOSFET on SOI for Low Power Applications

Faisal Bashir, Abdullah G. Alharbi, Sajad A. Loan

IEEE Journal of the Electron Devices Society > 2018 > 6 > 1 > 19 - 25

In this paper, we propose and simulate a novel Schottky barrier MOSFET (SB-MOSFET) with improved performance in comparison to the conventional SB-MOSFET. The proposed device employs charge plasma/electrostatic doping-based dopant segregation layers (DSLs) by using metal extensions (Hafnium) at the source and drain top and bottom edges. The metal hafnium induces charge plasma and hence realizes DSLs...

article

Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

Ashita, Sajad A. Loan, Abdullah G. Alharbi, Mohammad Rafat

Journal of Computational Electronics > 2018 > 17 > 3 > 977-985

In this paper, we propose and simulate two new structures of electron–hole bilayer tunnel field-effect transistors (EHBTFET). The proposed devices are n-heterogate with $$\hbox {M}_{1}$$ M1 as overlap gate, $$\hbox {M}_{2}$$ M2 as underlap gate and employs a high-k dielectric pocket in the drain underlap. Proposed structure 1 employs symmetric underlaps (Lgs = Lgd = Lu). The leakage analysis of...

article

Design and simulation of a doping-less charge plasma based enhancement mode GaN MOSFET

Sumit Verma, Sajad A. Loan, Abdulrahman M. Alamoud

Journal of Computational Electronics > 2018 > 17 > 1 > 256-264

In this work, we design and simulate a doping-less normally OFF/enhancement mode GaN based MOSFET. The novelty of the device is that it uses the charge plasma concept to induce n type charge plasma in an undoped GaN film, by employing metal electrodes, to realize source and drain regions of a GaN MOSFET. The proposed device is not a hetero-structure device, like the conventional GaN/AlGaN MOSFET and...

chapter

A junctionless inverted-TFET with increased ON-current and reduced ambipolarity

M. Ehteshamuddin, Sajad A. Loan, M. Rafat, Abdullah G. Alharbi

2017 8th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON) > 618 - 621

2017 8th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON)

In this paper, we simulate and investigate a novel Tunnel Field-Effect Transistor (TFET) using the charge plasma concept on the source side. Herein, an inverted p-type source is created to form a p+-n tunneling diode structure on a uniformly n-type doped thin silicon film, hence named, Inverted-TFET (I-TFET). Using calibrated simulations, we verify that the Ion is boosted (□ 20 times) in the proposed...

chapter

Enhanced subthreshold characteristic in SOI MOSFET with non-uniform drain doping profile

M. Ehteshamuddin, Sajad A. Loan, Mohd Haris, M. Rafat

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS) > 1 - 4

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)

In this paper, we provide an efficient method to improve the subthreshold characteristic of silicon-on-insulator (SOI) MOSFET using a vertical non-uniform doping profile for the drain region. Two different structures are simulated: uniform-drain (UD) and gaussian-drain (GD) SOI MOSFET and results are compared. Gaussian distribution function parameters such as peak doping density (N_p) and standard...

chapter

A novel finbox EHBTFET for low power applications

Ashita, Sajad A. Loan, Mohammad Rafat

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS) > 1 - 4

2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS)

In this work, for the first time we propose a Germanium on FinBOX based structure for an Electron-Hole Bilayer Tunnel FET (FB-EHBTFET) including Quantum Effects. The structure provides improved OFF state leakage suppression of more than five orders without the need of gated underlap that is required in the conventional EHBTFET and Fin EHBTFET. This reduces the device size by ∼25% compared to the Fin...

article

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

Sunil Kumar, Sajad A. Loan, Abdulrahman M. Alamoud

Superlattices and Microstructures > 2017 > 104 > C > 271-281

In this work we propose and simulate a compact nanoscaled transmission gate (TG) employing a single Schottky barrier based transistor in the transmission path and a single transistor based Sajad-Sunil-Schottky (SSS) device as an inverter. Therefore, just two transistors are employed to realize a complete transmission gate which normally consumes four transistors in the conventional technology. The...

chapter

Charge plasma based partial-ground-plane-MOSFET on selective buried oxide (SELBOX)

Faisal Bashir, Sajad A Loan, Asim Majeed Murshid, Abdulrahman M. Alamoud

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) > 1 - 3

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

In this work, we propose a novel charge plasma based partial ground plane selective buried oxide MOSFET (CP-PGP-SELBOX-MOSFET). In the proposed device source, drain regions and the partial ground planes (PGPs) have been realized by using metals of different work-functions and not by the conventional method of doping. A two dimensional (2D) simulation study has revealed that the magnitude of the short-channel...

article

Design of a novel high performance Schottky barrier based compact transmission gate

Sunil Kumar, Sajad A. Loan, Abdulrahman M. Alamoud

Superlattices and Microstructures > 2016 > 92 > C > 337-347

In this work, we propose and simulate a novel single transistor based transmission gate. The proposed device is a double gate Schottky device employing a stack of platinum silicide and erbium silicide materials to realize metal source and drain regions. The novelty of the proposed device lies in its ability to realize both n and p type modes simultaneously, which is normally being realized by a parallel...

chapter

Schottky barrier based compact transmission gate: A simulation study

Abdulrahman M. Alamoud, Sunil Kumar, Sajad A Loan, Asim M. Murshid

2016 3rd International Conference on Devices, Circuits and Systems (ICDCS) > 120 - 123

2016 3rd International Conference on Devices, Circuits and Systems (ICDCS)

chapter

A novel hybrid doping based SOI MOSFET

Sunil Kumar, Asim M. Murshid, Sajad A Loan

2016 3rd International Conference on Devices, Circuits and Systems (ICDCS) > 190 - 192

2016 3rd International Conference on Devices, Circuits and Systems (ICDCS)

In this paper, we propose a novel nano scale SOI MOSFET with hybrid doping. In the proposed device, the source of the transistor is conventionally doped while drain doping is controlled electrically by changing voltage level at an additional gate (SG) on one side of the main gate (MG). When a positive voltage at the side gate is applied, the device acts as a NMOS transistor. The hybrid doped NMOS...

article

A novel double gate metal source/drain Schottky MOSFET as an inverter

Sajad A. Loan, Sunil Kumar, Abdulrahman M. Alamoud

Superlattices and Microstructures > 2016 > 91 > C > 78-89

In this work, we propose and simulate a novel structure of a double gate metal source/drain (MSD) Schottky MOSFET. The novelty of the proposed device is that it realizes a complete CMOS inverter action, which is actually being realized by the combination of two n and p type MOS transistors in the conventional CMOS technology. Therefore, the use of this device will significantly reduce the transistor...

chapter

Investigation of a Multizone Drift Doping Based Lateral Bipolar Transistor on Buried Oxide Thick Step

Sajad A. Loan, S. Qureshi, S. Sundar Kumar Iyer

Lecture Notes in Electrical Engineering > Advances in Electrical Engineering and Computational Science > 23-32

A 2D numerical simulation study of a multizone step doped lateral bipolar junction transistor (LBJT) on buried oxide thick step (BOTS) is performed. The combination of multizone doping and BOTS has been used for increasing the breakdown voltage of the device. The steps in doping and step in oxide result in the creation of additional electric field peaks in the collector drift region which increases...

Publication date

Last 3 years (6)

Close

Date range setting

Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.

From:

To:
Set your own date range

Publication type

article (17)
book (15)

Keywords

CHARGE PLASMA (9)
LOGIC GATES (6)
PERFORMANCE EVALUATION (6)
MOSFET (5)
PLASMAS (5)
CUTOFF FREQUENCY (4)
DOPING (4)
DOPINGLESS (4)
FUZZY PROCESSOR (4)
LOW POWER (4)
SUBTHRESHOLD SLOPE (4)
BREAKDOWN VOLTAGE (3)
CNTFET (3)
INFERENCE (3)
LATERAL BIPOLAR JUNCTION TRANSISTOR (3)
METALS (3)
SCHOTTKY BARRIER (3)
SILICON-ON-INSULATOR (3)
SOI (3)
TFET (3)
VLSI DESIGN (3)
BAND-TO-BAND TUNNELING (BTBT) (2)
BILAYER TFET (2)
BURIED OXIDE (2)
CARBON NANOTUBES (2)
CURRENT CONVEYORS (2)
GATE ENGINEERING (2)
ION IMPLANTATION (2)
SEMICONDUCTOR PROCESS MODELING (2)
SILICON (2)
SWITCHING PERFORMANCE (2)
TFETS (2)
THERMAL ANALYSIS (2)
TRANSMISSION GATE (2)
TUNNELING (2)
2DEG (1)
2DHG (1)
ACCELERATORS (1)
ACTIVE GROUNDED INDUCTOR AND FILTERS (1)
AMBIPOLAR CONDUCTION (1)
AMBIPOLARITY (1)
AMBIPOLARITY SUPPRESON (1)
ARTIFICIAL INTELLIGENCE (1)
BAND‐TO‐BAND TUNNELING (BTBT) (1)
BICMOS INTEGRATED CIRCUITS (1)
BIPOLAR TRANSISTORS (1)
BREAKDOWN VOLTAGE (BV) (1)
BTBT (1)
BURIED OXIDE THICK STEP (1)
CALIBRATION (1)
CAPACITANCE (1)
CARBON NANOTUBE (1)
CAVET POLARIZATION ENGINEERING (1)
CENTER OF GRAVITY (1)
CMOS (1)
CONVOLUTIONAL NEURAL NETWORKS (1)
CURRENT DENSITY (1)
CUT‐OFF FREQUENCY (1)
DC GAIN (1)
DEEP NEURAL NETWORK (1)
DEFUZZIFICATION (1)
DELAY (1)
DENSITY GRADIENT (DG) (1)
DENSITY GRADIENT MODEL (1)
DIGITAL CIRCUITS (1)
DOPING JUNCTION (1)
DOUBLE GATE (1)
DSL (1)
DUAL OXIDE (1)
ELECTROSTATIC DOPING (ED) (1)
ELECTROSTATICALLY DOPED (1)
FIELD EFFECT TRANSISTORS (1)
FIN CHANNEL (1)
FINBOX (1)
FLUCTUATIONS (1)
FPGA (1)
GALLIUM NITRIDE (1)
GAN (1)
GATE OVER SOURCE (1)
GATED UNDERLAPS (1)
GAUSSIAN DOPING (1)
GERMANIUM (1)
HEAT SINK (1)
HETEROSTRUCTURE (1)
III–V (1)
III–V SEMICONDUCTOR (1)
IONS (1)
JLTFET (1)
JUNCTIONS (1)
LATERAL BJT (1)
LATERAL POCKET (1)
LEAKAGE CURRENTS (1)
MACHINE LEARNING (1)
MEMBERSHIP FUNCTION (1)
METAL SILICIDES (1)
METAL SOURCE/DRAIN (1)
MIXED MODE SIMULATION (1)
MULTIZONE DOPING (1)
MULTIZONE STEP (1)
NORMALLY OFF (1)
more

Data set

ieee (16)
Wiley (6)
Elsevier (5)
Springer (5)

INFONA - science communication portal

Search results for: Sajad A. Loan

High performance accelerators for deep neural networks: A review

Heterodielectric oxide‐engineered single‐lateral pocket‐based gated source TFET

CNTFET‐based active grounded inductor using positive and negative current conveyors and applications

Pseudo Split Gate In₀_.₅₃Ga₀_.47As/InP Hetero‐Junction Tunnel FET: Design and Analysis

CNTFET based class AB current conveyor II: Design, analysis and waveform generator applications

Electrostatically doped drain engineered DG‐TFET: Proposal and analysis

A normally OFF GaN CAVET and its thermal and trap analysis

Electrostatically Doped DSL Schottky Barrier MOSFET on SOI for Low Power Applications

Ambipolar leakage suppression in electron–hole bilayer TFET: investigation and analysis

Design and simulation of a doping-less charge plasma based enhancement mode GaN MOSFET

A junctionless inverted-TFET with increased ON-current and reduced ambipolarity

Enhanced subthreshold characteristic in SOI MOSFET with non-uniform drain doping profile

A novel finbox EHBTFET for low power applications

A novel nanoscaled Schottky barrier based transmission gate and its digital circuit applications

Charge plasma based partial-ground-plane-MOSFET on selective buried oxide (SELBOX)

Design of a novel high performance Schottky barrier based compact transmission gate

Schottky barrier based compact transmission gate: A simulation study

A novel hybrid doping based SOI MOSFET

A novel double gate metal source/drain Schottky MOSFET as an inverter

Investigation of a Multizone Drift Doping Based Lateral Bipolar Transistor on Buried Oxide Thick Step

Filter options

Publication date

Publication type

Keywords

Data set

Journal

INFONA - science communication portal

Search results for: Sajad A. Loan

Add recipient

Sending message cancelled

Are you sure you want to cancel sending this message?

Send message

Filter options

Publication date

Date range setting

Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.

Publication type

Keywords

Data set

Journal

Reporting an error / abuse

Sending the report failed

Accessibility options