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Photon Emission Microscopy is the most widely used mainstream defect isolation technique in failure analysis labs. It is easy to perform and has a fast turnaround time for results. However, interpreting a photon emission micrograph to postulate the suspected defect site accurately is challenging when there are multiple abnormal hotspots and driving nets involved. This is commonly encountered in dynamic...
Software scan diagnosis has been the de facto approach to narrow down possible defect locations in logic circuits by virtue of its speed and effectiveness. However, this capability is not supported for all product yield engineering and custom electrical failure analysis is naturally relied on. By this approach, unless the defects are gross, fault localization of internal logical nodes can be challenging...
Deoxyribonucleic Acid (DNA) sequence alignment is essentially a way of comparing two or more DNA sequences with aim to find regions of similarities among them. The Smith-Waterman (SW) algorithm is a local alignment algorithm which is able to identify mutation in DNA sequences. However, the aforementioned algorithm tends to be slower in computation of long DNA sequences. Over decades ago, Field Programmable...
It has always been a challenge to identify the failure mechanism of electrical overstress and latch-up failures due to misleading failure modes observed from electrical fault isolation. A Latch-up failure event involving an I/O cell of a SoC device is investigated. The root cause is determined by combining failure analysis, layout and commonality studies. It is found that the presence of abutting...
Embedded memories modules are one of the core components in System-on-a-Chip (SoC) device. For memory built-in self-test (MBIST) failures, bitmapping tool is normally used to locate the defect location. This paper demonstrates the effectiveness in the use of dynamic photon emission microscopy (PEM) analysis as an alternative method to debug MBIST failures. We also show how an additional failure characterization...
Pulsed-LADA is found to play an important role in the advancement of next-generation LADA and it is reported that tens of μs pulses with 10 kHz frequency is sufficient to observe enhancements in carrier injection. Electrically-enhanced LADA (EeLADA), based on pulsed-LADA, is introduced as a new fault localization method capable to overcome current limitation of Laser Assisted Device Alteration (LADA)...
Boundary scan test failures in the early phase of integrated circuit device yield engineering suggest fundamental manufacturing weaknesses and require fast response to fix the I/O connectivity., without which., chip functionality cannot be validated further. This paper presents a complete wafer-level workflow for JTAG-based boundary scan debug. We also show how a tester-based fault isolation technique...
Scan diagnosis based fault isolation technique using Electronic Design Automation (EDA) software tool is highly effective and commonly adopted for product chain and logic yield learning. For every new device introduction, prior to implementation of scan diagnosis for yield ramp, it is necessary to validate the success and accuracy of the test patterns generated for diagnosis. The accuracy of the fail...
Conventional software scan diagnosis using Electronic Design Automation (EDA) tools and hardware diagnosis using frequency mapping technique, are established methodologies for broken scan chains fault isolation. This work proposes a diagnostic workflow that integrates both methodologies to enhance accuracy and reduce turnaround time for debug. Experimental results are presented to demonstrate the...
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