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This paper describes a failure analysis on a commercial MEMS microphone after a test according to the standard of Mil-Std-883. With the help of test and a finite element simulation, we find that the studied MEMS part of the microphone can survive a stress limit above 20000g normal to the diaphragm plane. Under a constant acceleration high to 30000g, the diaphragm breaks and the devices fail.
The thermal stress in dual-damascene Cu interconnects with different via geometry and dielectric materials combination was simulated using the finite element method. The simulation results are presented to show that a small via linked to a wide and large Cu block increases the risk of electro-migration and stress migration failure. Vias in cylinders will drastically reduce thermal stress of the entire...
In this work, HCI effect of PMOS FETs was studied. For a given drain bias, electron trapping is the dominant degradation mechanism for a gate bias close to 20% of the drain bias. A maximum gate current is seen under this bias condition. Hole trapping is dominant when the gate bias is equal to the drain bias where drain current is the maximum. Electron trapping enhances PMOS driving current or Idsat...
The photo-induced instability of amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) is investigated. Device characteristics under white light illumination with various intensities and its spontaneous recovery at room temperature after illumination are observed. All the observed phenomena, especially the variation of threshold voltage and subthreshold swing, are explained by a simple model...
The electrical characteristics and reliability of the Hf-In-Zn-O (HIZO) MIS capacitor with a microporous SiO2-based electric-double-layer (EDL)/HfO2 stack gate dielectrics were investigated. Experimental results indicated that the HfO2 interlayer could effectively improve the interface quality. Moreover, enhanced reliability of the HIZO MISCAP with EDL/HfO2 stack gate was observed with an elevated...
For the realization of modern integrated circuits new interconnect structures like through-silicon-vias and solder bumps, together with complex multilevel 3D interconnect structures are gaining importance. The application of these new structures unavoidably rises different reliability issues like thermal gradients, electromigration, and stressmigration. In this paper we apply state-of-the art TCAD...
In the paper an evaluate structure was designed to investigate the degradation of gate metal in PHEMTs, and it can be used to separately appraise the resisted electromigration levels of the evaporated Ti/Pt/Au and the electroplated Au. The results show that the electromigration resistant level of electroplated Au of Ti/Pt/Au - Au is at least four times lower than that of the evaporated Ti/Pt/Au. For...
This paper reports the research of applying the worst stress condition of thick gate oxide LDMOSFET hot carrier reliability. Based on electrical characteristic and hot carrier degradation investigation, the worst stress condition selection and failure mechanism are discussed and then the reasonable stress condition is proposed in this paper.
Detection of electrical leakage in semiconductor devices indicates presence of electrical paths between junctions of p-doped and n-doped silicon, if no other physical abnormality is observed. This paper describes the use of advanced failure analysis tools to precisely locate and visualize crystalline defects in silicon that have caused electrical failure.
A novel technique of the on-site and real-time gamma ray radiation response analysis for semiconductor dies is proposed in the paper. Fundamental analysis of the die's radiation effects were demonstrated using the pulse current-voltage, the pulse capacitance-voltage and the pulse On-The-Fly measurements based on a probe station testing system which contains a lead container and a 10GBq 137Cs source...
Block Random Access Memory (BRAM) is a dedicated 18K/36Kbits hard logic configurable memory module embedded in Field Programmable Gate Array (FPGA) devices. BRAMs can be inferred as First In, First Out (FIFO) buffers, single or dual port, and cascading memory blocks accessed via by-1, 2, 4, 9,18, and 36 modes. Physical failure analysis (PFA) of intermittent read and write failures evident only at...
As the development of VLSI and scaling down & multi-metal-layer of semiconductor devices, there was the obstacle for failure analysis (FA) from front side of device. So, FA from backside was developed in microelectronics yield in recent years. As is known to all, we could capture clearer infrared (IR) image from backside as Si substrate was thinner. But if we needed higher resolution image with...
Determination of compositional distribution for solder material is of particular interest in the area of failure analysis, specifically in the investigation of various solder alloy formations during the joining processes and interconnection failures. In this paper, we explored several advanced techniques such as time-of-flight secondary ion mass spectrometry (TOF-SIMS), X-ray photoelectron spectroscopy...
Anomalous device degradation behavior of p-type polycrystalline silicon thin film transistors under negative gate bias stress is observed. In the first stage, negative gate bias instability dominates, resulting in negative threshold voltage (Vth) shift while in the second stage, negative charge generation induced by hot electrons happens, giving rise to positive Vth shift.
High voltage transistors (HV) are key devices to achieve the required high programming voltages in charge pumps and HV interfaces of EEPROM memory cells used for RFID applications. The combined use of EMMI, nanoprobing and wafer in-line monitoring on test structures was used to investigate the limits of low Breakdown (BD) voltages of these transistors in an embedded EEPROM CMOS 0.35µm technology.
Two new preparation methods of silicon substrates in the observation of micro-joint and micro-bumps failure mode were proposed in this study. One method is to use tilted grinding on 3DIC substrate to navigate the failed micro-joints. The other method can provide wider cross-section range by using ion polishing system studied in iST.
The small number of atoms involved in a 20nm conductor makes the conductor susceptible to the local variation in stress, grain structure and surrounding dielectric consistency. This leads to a larger variation in the performance of each metal line or via. At the same time, we increase the number of metal lines on a chip. The results is a complex failure distribution that will require design mitigation...
Integrated circuit chips of newer technology usually have a larger die size and an increase number of metallization. Hence, pure usage of polishing to remove the layers would induce severe edge rounding. An alternative method is proposed to decrease the polishing time for copper metallization removal while reducing edge rounding on the sample during sample preparation that will preserve the integrity...
This work investigates the generator properties of the Seebeck effect and the advantages of current detection via internal charge monitoring over external SMU measurement. Each of the two aspects increases precision in circuit diagnostics.
Emission, Laser Voltage Imaging, and Laser Voltage Probing data have been acquired from dual-gate fin field-effect-transistors (FinFETs). These optical probing techniques are applied to devices measuring 25 nm at their smallest dimension. Our results demonstrate that images and data collected from FinFET structures are qualitatively similar to those from a planar transistor.
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