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Adiabatic logic is an alternative architecture design style to reduce the power consumption of digital cores by using AC power supply instead of DC ones. The energy saving of the digital gates is strongly related to the efficiency of adiabatic AC power supplies. In this paper, we propose a resonant reversible power-clock supply design with four different phases. The resonance deviation between the...
In this study, we suggest a hierarchical model to investigate the electrical performance of carbon nanotube (CNT)- based interconnects. From the density functional theory, we have obtained important physical parameters, which are used in TCAD simulators to obtain the RC netlists. We then use these RC netlists for the circuit-level simulations to optimize interconnect design in VLSI. Also, we have...
We have performed statistical atomistic simulations with tight-binding approach to investigate the effects of randomly distributed mono-vacancy defects in metallic single-walled carbon nanotube (SWCNT) interconnects. We also extracted defective resistances from the atomistic simulations and performed circuit- level simulations to compare the performance of interconnects with and without defects. We...
Ever since the discovery of graphene, the 2D carbon structure material has been attracting a lot interest due its electrical, thermal and mechanical properties. Here, we investigate the carbon nanotubes (CNT), wrapping a 2D graphene sheet to form a 1D carbon structure. CNT has a Dirac-cone energy band, which makes it either a semiconductor or metal. With continuous aggressive scaling, the technology...
Carbon nanotubes (CNTs) present themselves as a viable material for on- and off-chip interconnect material due to their unique electrical, thermal and mechanical properties. The electro thermal properties of CNTs, including high Young's modulus, resiliency and low thermal expansion coefficient offer great advantage for reliable and strong interconnects, and even more so for local and global on-chip...
Due to its non-volatility, high access speed, ultra low power consumption and unlimited writing/reading cycles, STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) has emerged as the most promising candidate for the next generation universal memory. However, the process of commercialization of STT-MRAM is hampered by its poor reliability. Generally, these reliability issues are caused by...
Adiabatic logic is architecture design style which seems to be a good candidate to reduce the power consumption of digital cores. One key difference is that the power supply is also the clock signal. A lot of work on different adiabatic logic families has been done but the impact of the power supply and the power-clock network still remains to be studied. In this paper, we investigate the power-clock...
Spin transfer torque magnetic random access memory (STT-MRAM) is a potential candidate for next generation universal memory technology, which possesses the high density and cost benefits of DRAM, the high access speed of SRAM, the non-volatility of Flash, compatibility with CMOS and essentially unlimited endurance. However, STT-MRAM commercialization is hampered by the reliability issues, especially...
Carbon nanotubes (CNTs) due to their unique mechanical, thermal and electrical properties are being investigated as promising candidate material for on-chip and off-chip interconnects. The attractive mechanical properties of CNTs, including high Youngs modulus, resiliency and low thermal expansion coefficient offer great advantage for reliable and strong interconnects, and even more so for on-chip...
Three-dimensional Networks-on-Chip (3D NoCs) are based on Through-Silicon-Vias (TSV), which offer several advantages such as stacking, high throughput and energy efficiency. However, TSVs suffer from design process variations. On the other hand, designing purely asynchronous serializers enables reliable inter-tier communication with moderate performance overhead. A side benefit lies in the intrinsic...
This paper explores the benefits and costs of integrating an on-chip DC-DC converter as voltage regulator module for reliable power delivery networks (PDNs). We perform detailed time-domain and frequency analyses on PDNs to assess the impact of on-chip DC-DC converter on PDN impedance and overall supply noise behavior. As results show, the reliability of PDNs depends on the DC-DC converter design...
With integration density on-chip rocketing up, leakage power dominates the whole power budget of contemporary CMOS technology based memory, especially for SRAM based on-chip cache. To overcome the aggravating “power wall” issue, some emerging memory technologies such as STT-MRAM (Spin transfer torque magnetic RAM), PCRAM (Phase change RAM), and ReRAM(Resistive RAM) are proposed as promising candidates...
As the integration density rockets up for contemporary VLSI circuits, power consumption limits the scalability of technology advancement of CMOS. Spin transfer torque-magnetic random access memory (STT-MRAM), as one of the emerging non-CMOS technologies, has the promising prospect of low standby power, fast access speed and compatibility with the CMOS fabrication process. However, with the technology...
Due to the effects of the Moore's law, the process variations in current technologies are increasing and have a major impact on power and performance which results in parametric yield loss. Due to this, process variability and the difficulty of modeling accurately transistor behavior impede the dimensions scaling benefits. The Fully Depleted Silicon-On-Insulator (FDSOI) technology is one of the main...
Traditional CMOS integrated circuits suffer from elevated power consumption as technology node advances. A few emerging technologies are proposed to deal with this issue. Among them, STT-MRAM is one of the most important candidates for future on-chip cache design. However, most STT-MRAM based architecture level evaluations focus on in-plane magnetic anisotropy effect. In the paper, we evaluate the...
Ongoing technology scaling has increased delay defects in integrated circuits. Some of the delay defects are due to crosstalk, supply noise, process variations, etc. They degrade the performance and field reliability of circuits. However, testing the circuits with path delay patterns under worst-case conditions helps to detect such defects. Estimation of patterns with worst-case path delay becomes...
Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay...
Carbon nanotubes (CNTs) due their unique mechanical, thermal, and electrical properties are being investigated as promising candidate material for on-chip and off-chip interconnects. The attractive mechanical properties of CNTs, including high Youngs modulus, resiliency and low thermal expansion coefficient offer great advantage for reliable and strong interconnects, and even more so for 3D integration...
Through-Silicon Vias (TSVs) are the vertial vias that enable three-dimensional integration by providing shorter, faster and denser interconnects. In this work, we investigate their thermal properties and show that TSVs used for power and ground connections can suffer from high thermal dissipations, which can lead to reliability and timing errors. Due to nature of current flow on 3D ICs (i.e. from...
In order to improve performance and reduce cost, multi-processor system on chip (MPSoC) is increasingly becoming attractive. At the same time, 3D integration emerges as a promising technology for high density integration. 3D homogeneous MPSoCs combine the benefits of both. However, high current demand and large on-chip switching activity variations introduce severe power supply noises (PSN) for 3D...
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