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In a flip chip package (FCBGA), the presence of stress arising from the thermal mismatch between different materials is inevitable. It is a challenge for the packaging community to manage these stresses via careful selection of materials and design to achieve optimal performance and reliability of the integrated circuit. Finite Element Analysis (FEA) modeling for thermomechanical study is a widely...
In this work, a new empirical method is proposed to incorporate the initial substrate warpage into package stress simulation. As a first step, the bare substrate strip warpage characteristics were mapped. The out-of-plane displacements of the substrate strips were measured as a function of temperature using shadow moire technique. It was observed that the warpage values of the bare substrate vary...
In today's lead frame IC packages, the cost of lead frames account for one of the largest portion of material costs. Etched lead frames can cost 50% of the total package cost where as stamped frames can cost around 30%. With the increasing price trend of raw copper material in recent years, fueled by increasing demand on the use of copper (e.g. as an Au bonding wire replacement) this will inevitably...
In the automotive industry, electronic systems are expected to perform well under harsh reliability conditions. There is an emphasis to continuously develop ball grid array (BGA) IC packages that perform increasingly well with respect to board level temperature cycling reliability. This paper is a study of three No-Clean Polymer Flux (NCPF) materials and evaluation of their performance relative to...
In this paper, we report the experimental findings in the development of fine pitch flip chip interconnect using Au stud bumps on solder-on-pad finish substrate. The package consists of a 6 mm x 6 mm test die flip chip attached on a 10 mm times 10 mm substrate. Au stud bumping technology is employed to provide both the uncoined and coined stud bumps on the peripheral bond pads of test die at a pitch...
This paper demonstrates the application of finite element method in understanding the Cu/low-κ structure deformation mechanism during flip chip packaging. Four different modeling methods, detailed global model, global-local model, global-local model with homogenization procedure and sub-structure model were employed. In spite of the different modeling approaches, all models predicted the same maximum...
In this paper, we present the findings of a feasibility study to understand the impact of process and materials interaction in Pb-free flip chip package of 65nm Cu/low-k device. The concerns pertaining to Cu/low-k packaging were evaluated with successful demonstration of existing baseline assembly processes for low-k packaging. Several underfill materials were also evaluated in terms of processability...
In this paper, we discuss the impact of different flip chip interconnect schemes such as bump materials (SnAg2.5, SnAg3.5Cu0.5, Cu-pillar/SnAg2.5 cap, eNiAu, epl-Au and Au-stud), die-substrate coupling adhesives (underfill, ACF, ACP and NCP) and substrate pad finishes (ENIG, OSP and SOP) on the joint resistance and reliability performance of a common test vehicle. The integrity of the flip chip joints...
In this paper, we report the failure mode of a flip chip ball grid array package using Au stud bumps with non-conductive paste (NCP) as 1st level interconnect after temperature cycling (TC) testing. Finite element analysis (FEA) method was employed to investigate the failure mechanism and analyze the thermo-mechanical stress of the package. The highest stress location was calculated in the NCP near...
Flip chip assembly using non-conductive adhesives (NCAs) and anisotropic conductive adhesives (ACAs) is gaining importance and acceptance in electronics packaging industry. For this packaging technology, a variety of material combinations is possible involving different bump types and adhesives. One of the challenges is to select a robust flip chip joint configuration to meet desired reliability requirements...
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