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To improve the bSPIFET, the SA-bSPIFET which used self-aligned process had been proposed. However there are many characteristics of bSPIFET not yet be studied. This paper focuses on the misalignment of gate shift (GS) in a 30 nm bSPIFET. Based on 2D simulation, the misalignment of GS will influence the electrical characteristics causing the degradation of the short channel behaviour and the stability...
In this paper, for the first time, a novel devise-architecture namely multi-source/drain SOI MOSFET is proposed and compared with a conventional SOI MOSFET. According to the simulation result, our proposed transistor not only maintains the desirable short channel behaviour, but also enhances the on/off current ratio due to the multi-source/drain scheme.
This paper investigates the device behaviours of a pseudo tri-gate ultra-thin-channel vertical MOSFET with source/drain tie. For comparison two transistors are designed. According to the 2D simulation, our proposed structure can effectively enhance the drain current and the thermal stability, mainly due to the ultrathin channel (Tsi = 10 nm). The fabricated device have very low subthreshold swing...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
This work aims to examine and analyze carefully the effects of block oxide length (LBO) in a 40 nm multi-substrate-contact field-effect transistor (MSCFET). In addition, the proposed structure is based on the self-aligned (SA) gate-to-body technique. In the MSCFET design the two key parameters are the length and the height of the block oxide which are so sensitive to the short-channel effects (SCEs)...
In this paper, we present a new vertical MOS device having smart source/body contact (SSBVMOS). This vertical sidewall MOSFET possesses vertical channel, sidewall gate, and body passway which allow the conduction of both the generated carriers and heat. Thus, the fabricated device can achieve low self-heating effect and good suppression of the floating body effect without occupying excessive area.
The paper presents a non-classical architecture called the bottom gate MOSFET with source/drain tie (S/D-tied BG) to improve device reliability. S/D-tied BG MOSFET not only effectively reduce the effects of self-heating but also slightly suppress the short-channel effects.
This paper examines the effect of block oxide height (HBO) on a self-aligned (SA) source/drain-tied n-shaped block oxide field-effect transistor (S/D-tied nBOFET). According to the simulation results of a two-dimensional (2-D) numerical simulator DESSIS, the height of the block oxide is one of the important parameters for the suppression of short-channel effects (SCEs). Hence, the forming of HBO becomes...
What is silicon-on-insulator (SOI)? Why SOI? Because of the excellent short-channel effects (SCEs) immunity, SOI group is generally considered to be a very strong candidate in the end of the CMOS (complementary metal-oxide semiconductor) scaling, as compared to bulk silicon. This paper aims to propose a novel device architecture namely self-aligned (SA) Pi-shaped source/drain ultra-thin SOI MOS field-effect...
In this work, our main aim is to investigate the effects of source/drain thickness on the characteristics of self-aligned quasi-silicon-on-insulator metal-oxide semiconductor field-effect transistor with pi-shaped semiconductor conductive layer. According to the simulation results, we found that the short-channel characteristics and self-heating are much sensitive to the source/drain thickness. A...
A novel device architecture-the self-aligned pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) FET-is presented for the first time in the field of silicon-on-insulator (SOI) technology; this new device demonstrates how to decrease the self-heating effects in the SOI-based devices. Two-dimensional simulations show that the cost of building an S/D tie into the UTSOI-FET is a modest...
This paper presents a non-classical architecture called the bottom gate MOSFET with source/drain tie (S/D-tied BG) to achieve enhanced device reliability. According to the 2-D numerical simulation, the proposed structure can effectively reduce the effects of self-heating because of its source/drain-tied scheme, resulting in improved thermal stability. In addition, S/D-tied BG MOSFET not only diminishes...
This paper aims to comprehensively examine the electrical characteristics of a new silicon-on-insulator (SOI) device structure with source/drain (S/D) tie as a function of the block oxide height. According to the 2-D simulations, the height of the block oxide enclosing the silicon body is one of the key parameters for determining the device properties and their fluctuations. Additionally, the self-heating...
One of the key issues that block the development of silicon-on-insulator (SOI) CMOS technology is so-called self-heating effects (SHEs). In this paper, we have investigated the electrical characteristics of multi-substrate contact field-effect transistors (MSCFETs) depend on the gate length for the first time. The proposed structure of MSCFET can significantly diminish the thermal instability occurred...
In order to further simplify the process flow and eliminate the device misalignment of the Si-body to the poly gate in a bSPIFET (Si on partial insulator with block oxide field-effect transistor) [1], a new self-aligned (SA) process has been successfully developed. The aim of this work is to investigate the device behavior of SA-bSPIFET as a function of gate length. According to the simulation studies,...
In this study, the enhancement of pi-FET performance using optimized parameters is designed to investigate the electrical characteristics as a function of the BOI length (LBOI) under the body region. Additionally, the SOI devices (FDSOI-FET and UTBSOI-FET) are also designed for the comparison with the pi-FET by using ISE TCAD tools.
In the case of the fully depleted silicon-on-insulator (FDSOI) FET, it is a hard task for the suppression of short-channel effects (SCEs) without using the ultra-thin body type; unless some technical tricks (e.g., halo doping, threshold voltage adjustment, retrograde channel implant, ultra-shallow junction depth) are applied (Pawlak, 2006). The results of previous study showed that the pi-FET (quasi-SOI...
This paper presents a novel self-aligned fully depleted silicon-on-insulator field-effect transistor with block oxide (namely SA-bFDSOI) and we investigate its ultra-short channel and thermal characteristics for the first time. In the case of SA-bFDSOI, the misaligned problem caused by two different exposures via the mask in a bFDSOI can be totally overcome. Moreover, the recessed source/drain (S/D)...
For the purpose of performance improvement from bSPIFET (Si on partial insulator with block oxide field-effect transistor) technology [1], a self-aligned bSPIFET was proposed. However, a lot of electrical characteristics have not yet been studied in detail. This paper aims to investigate the device behaviour of self-aligned bSPIFET as a function of misaligned block oxide height. According to the TCAD...
In this work, a novel fully depleted silicon-on- insulator MOSFET with block oxide (bFDSOI) is proposed to investigate the influence of Si-body thickness on the characteristics of the device. Based on the two-dimensional (2-D) simulation results, the proposed structure exhibits better ultra-short-channel behavior such as reduced drain-induced barrier lowering (DIBL) and better subthreshold swing when...
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