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Neutron-induced multiple-bit upsets (MBU) in a 90 nm CMOS SRAM are examined using Monte-Carlo simulations. While the single-bit upset (SBU) cross section is nearly independent of angle, the probability of MBU increases for neutrons incident at grazing angles.
This paper presents a quasi delay insensitive (QDI) asynchronous circuit design paradigm -modified Null Convention Logic (NCL), for high single event upset (SEU) tolerance We investigate the behavior of the QDI circuit in the presence of SEUs, and propose a framework to evaluate the SEU sensitivity of the circuit. The modified NCL circuit can eliminate all SEUs in computational blocks if these SEUs...
Experimental thermal neutron and alpha soft error test results of a 4 Mbit SRAM fabricated on a 0.25 mum process are evaluated using Vanderbilt University's RADSAFE toolkit. The capabilities of the radiation transport code are demonstrated by accurately reproducing experimental results and predicting operational soft error rates for the memory.
The proposed microsystem architecture comprises two power sources, and a microbattery used as a storage unit ; a complete integrated circuit transforms and manages the harvested energy and interfaces the microbattery. The first source is a RF power receiver combined with a classical RF converter. The second micropower source is a 1V miniature thermogenerator based on sintered bismuth telluride thermoelements,...
3D Integration of patterned semiconductors circuits or/and integrated sensors requires some knowledge of vertical circuits stacking architecture and available technologies to realise expected by this integration performances. 3D architectures have emerged as serious contender in the challenge of functionality and potentiality increasing. Innovative circuit design, new advanced substrates, improved...
Analyses of ion-induced charge sharing effects at the 90 nm CMOS technology node are discussed. Two mechanisms leading to enhanced charge collection and increased soft error sensitivity are presented.
A continuous time analog interface for a capacitive accelerometer element is implemented. The integrated part of the interface includes an oscillator and readout circuitry excluding a controller and references. For the realized sensor, the minimum equivalent acceleration noise density of 400 ng/radicHz is measured. A full scale acceleration of plusmn1.5 g and a signal bandwidth of 300 Hz is achieved...
Accurate chip level timing analysis requires a careful modeling of interaction between logic drivers and interconnect wires. Existing static-timing analysis methodologies translate the actual loading and interconnect parasitics into a single effective capacitance. However, previous approaches to perform that translation capture the delay information only. They are not able to capture the slew information...
We present a simple MOSFET model which represents a MOSFET as a gate-modulated resistance. Such a model leads to a special structure in the circuit equations which lends itself to rapid evaluation. In spite of its simplicity, the model makes excellent predictions of waveform propagation with a minimum of characterization effort. The parameters of the model are well-correlated with major technology...
An efficient technique to establish a constant matrix with variable step-size multi-step formulas is presented for transient analysis of linear power grids. Instead of deriving new formulas with a constant leading coefficient, it is shown that, if the step change is relatively small, a constant matrix can also be obtained by carefully allocating the integration points and using the existing variable...
One of the biggest challenges for the VLSI circuits with 32-nm-technology nodes and beyond is to overcome the issue of catastrophic increases in power consumption due to short-channel effects (SCEs). Fortunately, "independent" double-gate (DG) FinFETs (named "4-terminal-FinFET" because of its four terminals; source, drain, gate 1 and gate 2) have a promising potential to overcome...
High dielectric constant (K) gate dielectrics have been intensively developed to overcome problems of transient charge trapping, threshold voltage shifts and Fermi level pinning of the gate electrode. Most of these problems can be traced to the effect of oxygen vacancies, whose role is summarized in this paper.
We compared electrical characteristics of TBCFET (Triple-Bridge-Channel MOSFET), MBCFET (Multi-Bridge-Channel MOSFET) and SBCFET (Single-Bridge-Channel MOSFET) with sub-20 nm gates. TBCFET is suitable for low-power application with 2.9 mA/um of on-state current and SNM (static noise margin) of 320 mV even at Vdd = 0.8V MBCFET and SBCFET, that are applicable to high-performance devices, show 4.17 mA/um...
In state-of-the-art Digital Signal Processing (DSP) and Graphics applications, multiplication is an important and computationally intensive operation, consuming a significant amount of delay. The final carry propagate hybrid adder inside a multiplier plays an important role in determining the performance of the multiplication block. This paper presents an algorithmic approach to generate the optimal...
Progresses in FinFET SRAM process technology are reviewed. The process technologies discussed in this paper are narrow and uniform fin formation, reduction of source/drain parasitic resistance, gate stack for threshold voltage control, integration scheme to build FinFET and planar FET on a wafer, and fin height tuning technique for beta-ratio control. These technologies are considered to enable the...
A novel VLSI array architecture for vector-scalar multiplication is introduced. It is based on a parameterized divide and conquer algorithm that uses optimal partitioning and redundancy removal for simultaneous computation of partial sums. Two variations of the proposed Parameterized Vector-Scalar Multiplier Architecture (PVSMA), namely PVSMA-A and PVSMA-AT, are implemented and compared to the parallel...
A novel 3D computational self-consistent electro-thermal modeling methodology is developed to more precisely analyze leakage currents in nanoscale FinFET devices. The coupled electro-thermal modeling is applied to compare the device performance of poly-Si gate and metal-gate DG-FinFET. Results show very high leakage current in band-edge metal-gate device and poly-Si gate device. Mid-gap metal-gate...
Effects of drift-region design on the hot-carrier reliability of n-channel integrated high-voltage lateral diffused MOS (LDMOS) transistors are investigated. LDMOS devices with various dosages of n-type drain drift (NDD) implant and various drift-region lengths (Ld) are studied. Results show that higher NDD dosage can reduce hot-carrier induced on-resistance (Ron) degradation. The shift in damage...
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