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Self-test and diagnosis is an inherent part of fault tolerance approaches, which are realized by active hardware redundancy. The test must be available in-field and has to provide a diagnostic resolution, which matches the repair function of the fault tolerance approach. Continuous development lead to ever fine grained repair functions, which require a growing diagnostic resolution. Typically, fault...
This paper describes a software-based technique for building heterogeneous fault tolerant multi-core systems, which are able to handle temporary and permanent hardware faults autonomously in two system layers. The fault tolerance technique relies on a single concept for adapting the binary code of the user application to the current fault state of a single core. Thereby this scheme is used either...
Nano-electronic circuits and systems with a minimum feature size of 45 nm and below exhibit an increasing variety of defect and fault mechanisms. Their rising sensitivity to radiation and coupling induced single and multiple event upsets is one problem, new or enhanced aging processes that lead to early lifetime failures (ELF) pose another threat. The compensation of transient fault effects is a well...
The design space of integrated circuits grows due to the need of fault recognition and error compensation. To meet reliability requirements, several reliability increasing methods have to be evaluated. We present a reliability estimation process which allows estimating the resulting reliability of a modified circuit without the need of synthesis. For further speed up, synthesis results after choosing...
Predictions for the properties of integrated circuits and systems fabricated in emerging nanotechnologies indicate a rising level of static and dynamic faults due to new fault mechanisms. Not only transient faults due to particle radiation are becoming a problem, but also wear-out effects on transistors and interconnects. While transient faults can be covered by well-known technologies such as error-correcting...
Technology forecasts concerning the development of CMOS technologies predict a higher level of intermittent faults due to radiation effects, but also a higher density of permanent fault effects due to inevitable parameter shifts and higher stress factors. For high production yield and long-term dependable operation, mechanisms of built-in self repair that can be used after production test and in the...
Fault diagnosis has recently become an important issue in IC production test because of the need to enforce high manufacturing yield. Furthermore, fault diagnosis is a pre-condition for any technology of built-in self repair that may be used in the field of application where long-time dependable systems are necessary. An "embedded" diagnostic self test has to get along with a minimum of...
Built-in self test (BIST) and built-in self repair (BISR) techniques have been developed for memory blocks in recent years. Such techniques are suited to enhance production yield, but also to facilitate long-term dependable circuits though self repair in the field of application. BISR for logic circuits has shown to be much more complex, for which only a few approaches have been published so far....
SystemC has been widely accepted for the description of electronic systems. An essential advantage of a SystemC description is the possibility of a built-in compiled-code simulation. Beyond the functional simulation for validation of a hardware design, there are additional requirements for an advanced simulation of faults in order to analyze the system behavior under fault conditions. The paper introduces...
Physical design for digital ICs, based on standard cells, has long been performed without explicit consideration of timing and power related to interconnects. With delays on wires more and more dominating the delays on logic paths, such design styles are becoming obsolete. What is needed is an iterative inclusion of power and timing aspects into the design flow for placement and routing, which yields...
Test technology development for processor-based Systems on a Chip (SoCs) has mainly focused on quality and cost of production test. More recently, test technologies that facilitate self test in the field of application are getting additional attention. Hardware-based built-in self test (BIST) is well understood for logic and for memory block, but can hardly cope with changing test strategies. We present...
Fault tolerant design has recently gained new attention due to the increasing volatility of nano-electronic circuits from transient fault effects. Latches and flip-flops are the potential sources of errors. Novel designs of fault-tolerant flip-flops encompass multiple latches, which can also be used to accommodate the double-latched scan for dynamic test. The resulting scan-path elements are fault-tolerant...
The ever-increasing complexity of systems on a chip (SoCs) has driven scan-based logic test technologies to their limits. Built-in self-test is one possible solution to overcome the problem. However, externally controlled test procedures that allow the re-use of existing testers and adaption to changing patterns seem to gain a higher level of industrial acceptance. Then a high degree of test pattern...
Main stream scan test technology development has focused on a cost-efficient usage of external testers in conjunction with minimized on-chip pattern generators. Alternatively, an on-chip test processor that works with highly compacted test patterns from a ROM device allows a software-based self test procedure in the field of application, e.g. during startup tests. Furthermore, such an approach may...
In this paper we describe a methodology to measure exactly the quality of fault-tolerant designs by combining fault-injection in high level design (HLD) descriptions with a formal verification approach. We utilize BDD based symbolic simulation to determine the coverage of online error-detection and -correction logic. We describe an easily portable approach, which can be applied to a wide variety of...
Systems on a chip (SoCs) typically consist of several processor devices, embedded memory blocks, application-specific logic blocks and complex interconnects. While embedded memory blocks are mostly equipped with built-in self test (BIST) capabilities, test methods for processors, logic blocks and interconnects are still topics of intensive research. Beyond production testing, SoCs in safety-critical...
Systems on a chip (SoCs) in safety-critical applications need features such as built-in self-test, on-line self-test and error compensation of transient faults. With ever-shrinking feature size, also built-in self-repair (BISR) may become a must. While BIST and BISR are well understood and frequently implemented for embedded memory blocks, BISR for random logic is by far an unsolved problem. Logic...
Technology forecasts predict that nanometer IC technologies do not yield large chip areas without non-functional transistors. Mechanism of redundancy and re-organization for self-repair at the transistor and gate level are required, which can effectively handle realistic fault effects in CMOS logic circuits
Fault simulation technology is essential key not only to the validation of test patterns for ICs and SoCs, but also to the analysis of system behavior under fault transient and intermittent faults. For this purpose, we developed a hierarchical fault simulation environment that uses structural VHDL models at the gate level, but is able to model embedded blocks in C++. With SystemC becoming a de-facto...
Systems on a chip (SoCs) that consist of one or several processor devices, other complex functional blocks, embedded memories plus multiple interconnects are a big challenge to design and test technology. The simulation of such complex systems under fault conditions is an open problem, since RTL simulators typically do not provide simple means of fault injection and high speed in combination. On the...
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